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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id vw16-20020a170907a71000b00a2ca97242d5sm601302ejc.120.2024.01.26.05.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:03:28 -0800 (PST) Date: Fri, 26 Jan 2024 14:03:27 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 6/6] target/riscv: Promote svade to a normal extension Message-ID: <20240126-a0cd03d186454ff0a98f7911@orel> References: <20240125195319.329181-1-dbarboza@ventanamicro.com> <20240125195319.329181-7-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240125195319.329181-7-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jan 25, 2024 at 04:53:19PM -0300, Daniel Henrique Barboza wrote: > From: Andrew Jones > > Named features are extensions which don't make sense for users to > control and are therefore not exposed on the command line. However, > svade is an extension which makes sense for users to control, so treat > it like a "normal" extension. The default is false, since QEMU has > always implemented hardware A/D PTE bit updating, so users must opt into > svade (or get it from a CPU type which enables it by default). > > Signed-off-by: Andrew Jones > Reviewed-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a56c2ff91d..4ddde25412 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1421,6 +1421,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > + MULTI_EXT_CFG_BOOL("svade", ext_svade, false), I forgot that the 'max' cpu type will ignore this off by default setting and enable svade by default. I'll send a v2 of this series where I ensure svade for 'max' also defaults false. Thanks, drew > MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), > @@ -1528,7 +1529,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > * and priv_ver like regular extensions. > */ > const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { > - MULTI_EXT_CFG_BOOL("svade", ext_svade, true), > MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), > > /* > @@ -2175,8 +2175,6 @@ static RISCVCPUProfile RVA22U64 = { > * Other named features that we already implement: Sstvecd, Sstvala, > * Sscounterenw > * > - * Named features that we need to enable: svade > - * > * The remaining features/extensions comes from RVA22U64. > */ > static RISCVCPUProfile RVA22S64 = { > @@ -2188,11 +2186,11 @@ static RISCVCPUProfile RVA22S64 = { > .ext_offsets = { > /* rva22s64 exts */ > CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), > - CPU_CFG_OFFSET(ext_svinval), > + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade), > > /* rva22s64 named features */ > CPU_CFG_OFFSET(ext_sstvecd), CPU_CFG_OFFSET(ext_sstvala), > - CPU_CFG_OFFSET(ext_sscounterenw), CPU_CFG_OFFSET(ext_svade), > + CPU_CFG_OFFSET(ext_sscounterenw), > > RISCV_PROFILE_EXT_LIST_END > } > -- > 2.43.0 >