Re: [PATCH 5/5] hw/cxl: Standardize all references on CXL r3.1 and minor updates

[Jonathan Cameron via <qemu-devel@nongnu.org>]

On Wed, 24 Jan 2024 12:58:19 -0800
fan <nifan.cxl@gmail.com> wrote:

> On Wed, Jan 24, 2024 at 01:48:14PM +0000, Jonathan Cameron wrote:
> > Previously not all references mentioned any spec version at all.
> > Given r3.1 is the current specification available for evaluation at
> > www.computeexpresslink.org update references to refer to that.
> > Hopefully this won't become a never ending job.
> > 
> > A few structure definitions have been updated to add new fields.
> > Defaults of 0 and read only are valid choices for these new DVSEC
> > registers so go with that for now.
> > 
> > There are additional error codes and some of the 'questions' in
> > the comments are resolved now.
> > 
> > Update documentation reference to point to the CXL r3.1 specification
> > with naming closer to what is on the cover.
> > 
> > For cases where there are structure version numbers, add defines
> > so they can be found next to the register definitions.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---  
> 
> There are several references to the spec is incorrect, other than that
> LGTM.
> 
> Search "Identify Memory Device (Opcode 4000h)" for inline comments.
Thanks for ploughing through all this!


> >      /* Store off everything to local variables so we can wipe out the payload */
> > @@ -760,7 +757,7 @@ static CXLRetCode cmd_logs_get_log(const struct cxl_cmd *cmd,
> >      return CXL_MBOX_SUCCESS;
> >  }
> >  
> > -/* 8.2.9.5.1.1 */
> > +/* CXL r3.1 Section 8.2.9.8.1.1: Identify Memory Device (Opcode 4000h) */  
> 
> Should be 8.2.9.9.1.1

Oops. I think I had the 3.0 spec open by accident when doing some of these.
Good catch - I'll fix these all up and send a v2.