From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Thomas Huth" <thuth@redhat.com>,
qemu-s390x@nongnu.org, qemu-riscv@nongnu.org,
"Eduardo Habkost" <eduardo@habkost.net>,
kvm@vger.kernel.org, qemu-ppc@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Vladimir Sementsov-Ogievskiy" <vsementsov@yandex-team.ru>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Huacai Chen" <chenhuacai@kernel.org>
Subject: [PATCH v2 13/23] target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro
Date: Fri, 26 Jan 2024 23:03:55 +0100 [thread overview]
Message-ID: <20240126220407.95022-14-philmd@linaro.org> (raw)
In-Reply-To: <20240126220407.95022-1-philmd@linaro.org>
Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.c | 11 +++-------
target/mips/gdbstub.c | 6 ++----
target/mips/kvm.c | 27 +++++++++----------------
target/mips/sysemu/physaddr.c | 3 +--
target/mips/tcg/exception.c | 3 +--
target/mips/tcg/op_helper.c | 3 +--
target/mips/tcg/sysemu/special_helper.c | 3 +--
target/mips/tcg/sysemu/tlb_helper.c | 6 ++----
target/mips/tcg/translate.c | 3 +--
9 files changed, 21 insertions(+), 44 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a0023edd43..d9c0c0dada 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -80,8 +80,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
@@ -137,8 +136,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs)
static bool mips_cpu_has_work(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
bool has_work = false;
/*
@@ -428,10 +426,7 @@ static void mips_cpu_reset_hold(Object *obj)
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
- MIPSCPU *cpu = MIPS_CPU(s);
- CPUMIPSState *env = &cpu->env;
-
- if (!(env->insn_flags & ISA_NANOMIPS32)) {
+ if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
#if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips;
#else
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 62d7b72407..169d47416a 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -25,8 +25,7 @@
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
@@ -78,8 +77,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
target_ulong tmp;
tmp = ldtul_p(mem_buf);
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 15d0cf9adb..6c52e59f55 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -63,8 +63,7 @@ int kvm_arch_irqchip_create(KVMState *s)
int kvm_arch_init_vcpu(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
@@ -460,8 +459,7 @@ static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,
*/
static int kvm_mips_save_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err, ret = 0;
@@ -502,8 +500,7 @@ static int kvm_mips_save_count(CPUState *cs)
*/
static int kvm_mips_restore_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err_dc, err, ret = 0;
@@ -590,8 +587,7 @@ static void kvm_mips_update_state(void *opaque, bool running, RunState state)
static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
@@ -670,8 +666,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
static int kvm_mips_get_fpu_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
@@ -751,8 +746,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
(void)level;
@@ -974,8 +968,7 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
static int kvm_mips_get_cp0_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
@@ -1181,8 +1174,7 @@ static int kvm_mips_get_cp0_registers(CPUState *cs)
int kvm_arch_put_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
struct kvm_regs regs;
int ret;
int i;
@@ -1217,8 +1209,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
int kvm_arch_get_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
struct kvm_regs regs;
int i;
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
index 05990aa5bb..56380dfe6c 100644
--- a/target/mips/sysemu/physaddr.c
+++ b/target/mips/sysemu/physaddr.c
@@ -230,8 +230,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index da49a93912..13275d1ded 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -79,8 +79,7 @@ void helper_wait(CPUMIPSState *env)
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->active_tc.PC = tb->pc;
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index 98935b5e64..b57baa7ec1 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -279,8 +279,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int error_code = 0;
int excp;
diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
index 93276f789d..7934f2ea41 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -90,8 +90,7 @@ static void debug_post_eret(CPUMIPSState *env)
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 4ede904800..6c48c4fa80 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -910,8 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr physical;
int prot;
int ret = TLBRET_BADADDR;
@@ -1346,8 +1345,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (cpu_mips_hw_interrupts_enabled(env) &&
cpu_mips_hw_interrupts_pending(env)) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 13e43fa3b6..e74b98de1c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15628,8 +15628,7 @@ void mips_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
env->active_tc.PC = data[0];
env->hflags &= ~MIPS_HFLAG_BMASK;
--
2.41.0
next prev parent reply other threads:[~2024-01-26 22:07 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-26 22:03 [PATCH v2 00/23] hw, target: Prefer fast cpu_env() over slower CPU QOM cast macro Philippe Mathieu-Daudé
2024-01-26 22:03 ` [PATCH v2 01/23] hw/acpi/cpu: Use CPUState typedef Philippe Mathieu-Daudé
2024-01-27 4:14 ` Richard Henderson
2024-01-27 11:34 ` Zhao Liu
2024-01-26 22:03 ` [PATCH v2 02/23] scripts/coccinelle: Add cpu_env.cocci_template script Philippe Mathieu-Daudé
2024-01-27 5:01 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 03/23] bulk: Call in place single use cpu_env() Philippe Mathieu-Daudé
2024-01-27 4:19 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 04/23] target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro Philippe Mathieu-Daudé
2024-01-27 4:23 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 05/23] target/arm: " Philippe Mathieu-Daudé
2024-01-27 4:24 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 06/23] target/avr: " Philippe Mathieu-Daudé
2024-01-27 4:25 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 07/23] target/cris: " Philippe Mathieu-Daudé
2024-01-27 4:27 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 08/23] target/hppa: " Philippe Mathieu-Daudé
2024-01-27 4:28 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 09/23] target/i386/hvf: Use CPUState typedef Philippe Mathieu-Daudé
2024-01-27 4:29 ` Richard Henderson
2024-01-27 13:47 ` Zhao Liu
2024-01-26 22:03 ` [PATCH v2 10/23] target/i386: Prefer fast cpu_env() over slower CPU QOM cast macro Philippe Mathieu-Daudé
2024-01-27 4:31 ` Richard Henderson
2024-01-27 10:07 ` David Woodhouse
2024-01-27 12:21 ` Zhao Liu
2024-01-28 16:16 ` Philippe Mathieu-Daudé
2024-01-26 22:03 ` [PATCH v2 11/23] target/m68k: " Philippe Mathieu-Daudé
2024-01-27 4:32 ` Richard Henderson
2024-01-29 4:23 ` Thomas Huth
2024-01-26 22:03 ` [PATCH v2 12/23] target/microblaze: " Philippe Mathieu-Daudé
2024-01-27 4:33 ` Richard Henderson
2024-01-26 22:03 ` Philippe Mathieu-Daudé [this message]
2024-01-27 4:35 ` [PATCH v2 13/23] target/mips: " Richard Henderson
2024-01-26 22:03 ` [PATCH v2 14/23] target/nios2: " Philippe Mathieu-Daudé
2024-01-27 4:37 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 15/23] target/openrisc: " Philippe Mathieu-Daudé
2024-01-27 4:37 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 16/23] target/ppc: " Philippe Mathieu-Daudé
2024-01-27 4:38 ` Richard Henderson
2024-01-26 22:03 ` [PATCH v2 17/23] target/riscv: " Philippe Mathieu-Daudé
2024-01-27 4:43 ` Richard Henderson
2024-01-26 22:04 ` [PATCH v2 18/23] target/rx: " Philippe Mathieu-Daudé
2024-01-27 4:44 ` Richard Henderson
2024-01-26 22:04 ` [PATCH v2 19/23] target/s390x: " Philippe Mathieu-Daudé
2024-01-27 4:46 ` Richard Henderson
2024-01-29 4:25 ` Thomas Huth
2024-01-26 22:04 ` [PATCH v2 20/23] target/sh4: " Philippe Mathieu-Daudé
2024-01-27 4:48 ` Richard Henderson
2024-01-26 22:04 ` [PATCH v2 21/23] target/tricore: " Philippe Mathieu-Daudé
2024-01-27 4:50 ` Richard Henderson
2024-01-28 10:34 ` Bastian Koppelmann
2024-01-26 22:04 ` [PATCH v2 22/23] target/xtensa: " Philippe Mathieu-Daudé
2024-01-27 4:51 ` Richard Henderson
2024-01-26 22:04 ` [PATCH v2 23/23] target/sparc: " Philippe Mathieu-Daudé
2024-01-27 4:52 ` Richard Henderson
2024-01-29 21:43 ` Mark Cave-Ayland
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