* [PATCH 00/33] tcg patch queue, pre-pull
@ 2024-01-28 4:41 Richard Henderson
2024-01-28 4:41 ` [PATCH 01/33] cpu-exec: simplify jump cache management Richard Henderson
` (34 more replies)
0 siblings, 35 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel
Collect some patch sets, cherry-pick from others, with a few
changes of my own. Patches that lack review:
26-include-qemu-Add-TCGCPUOps-typedef-to-typedefs.h.patch
27-target-loongarch-Constify-loongarch_tcg_ops.patch
28-accel-tcg-Use-CPUState.cc-instead-of-CPU_GET_CLASS-i.patch
31-accel-tcg-Inline-need_replay_interrupt.patch
r~
Anton Johansson (11):
include/exec: Move vaddr defines to separate file
hw/core: Include vaddr.h from cpu.h
target: Use vaddr in gen_intermediate_code
include/exec: Use vaddr in DisasContextBase for virtual addresses
include/exec: typedef abi_ptr to vaddr
target: Uninline cpu_mmu_index()
target: Uninline cpu_get_tb_cpu_state()
include/exec: Move PAGE_* macros to common header
include/exec: Move cpu_*()/cpu_env() to common header
include/hw/core: Move do_interrupt in TCGCPUOps
include/hw/core: Remove i386 conditional on fake_user_interrupt
Ilya Leoshkevich (8):
linux-user: Allow gdbstub to ignore page protection
tests/tcg: Factor out gdbstub test functions
tests/tcg: Add the PROT_NONE gdbstub test
target: Make qemu_target_page_mask() available for *-user
accel/tcg: Make use of qemu_target_page_mask() in perf.c
tcg: Make tb_cflags() usable from target-agnostic code
accel/tcg: Remove #ifdef TARGET_I386 from perf.c
accel/tcg: Move perf and debuginfo support to tcg/
Paolo Bonzini (1):
cpu-exec: simplify jump cache management
Philippe Mathieu-Daudé (9):
accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD
accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson
accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy()
accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec()
accel/tcg: Un-inline icount_exit_request() for clarity
accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler
target/i386: Extract x86_need_replay_interrupt() from accel/tcg/
accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler
target/i386: Extract x86_cpu_exec_halt() from accel/tcg/
Richard Henderson (4):
include/qemu: Add TCGCPUOps typedef to typedefs.h
target/loongarch: Constify loongarch_tcg_ops
accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c
accel/tcg: Inline need_replay_interrupt
accel/tcg/tb-jmp-cache.h | 8 +-
accel/tcg/tcg-accel-ops.h | 4 +-
include/exec/cpu-all.h | 49 ----
include/exec/cpu-common.h | 82 ++++++-
include/exec/cpu_ldst.h | 4 +-
include/exec/exec-all.h | 6 -
include/exec/translation-block.h | 6 +
include/exec/translator.h | 8 +-
include/exec/vaddr.h | 18 ++
include/hw/core/cpu.h | 7 +-
include/hw/core/tcg-cpu-ops.h | 19 +-
include/qemu/typedefs.h | 1 +
{accel => include}/tcg/debuginfo.h | 4 +-
{accel => include}/tcg/perf.h | 4 +-
target/alpha/cpu.h | 20 --
target/arm/cpu.h | 16 --
target/avr/cpu.h | 25 --
target/cris/cpu.h | 14 --
target/hexagon/cpu.h | 21 --
target/hppa/cpu.h | 55 -----
target/i386/cpu.h | 21 --
target/i386/tcg/helper-tcg.h | 2 +
target/loongarch/cpu.h | 24 --
target/m68k/cpu.h | 20 --
target/microblaze/cpu.h | 23 --
target/mips/cpu.h | 14 --
target/mips/tcg/translate.h | 3 +-
target/nios2/cpu.h | 18 --
target/openrisc/cpu.h | 22 --
target/ppc/cpu.h | 21 --
target/riscv/cpu.h | 6 -
target/rx/cpu.h | 14 --
target/s390x/cpu.h | 55 -----
target/sh4/cpu.h | 25 --
target/sparc/cpu.h | 61 -----
target/tricore/cpu.h | 17 --
target/xtensa/cpu.h | 73 ------
accel/tcg/cpu-exec.c | 223 ++++++++----------
accel/tcg/tcg-accel-ops-mttcg.c | 4 +-
accel/tcg/tcg-accel-ops-rr.c | 4 +-
accel/tcg/tcg-accel-ops.c | 4 +-
accel/tcg/translate-all.c | 2 +-
bsd-user/signal.c | 4 +-
cpu-target.c | 76 ++++--
hw/core/loader.c | 2 +-
linux-user/elfload.c | 2 +-
linux-user/exit.c | 2 +-
linux-user/main.c | 2 +-
linux-user/signal.c | 4 +-
system/physmem.c | 5 -
system/vl.c | 2 +-
target/alpha/cpu.c | 21 +-
target/alpha/translate.c | 2 +-
target/arm/cpu.c | 7 +-
target/arm/tcg/cpu32.c | 2 +-
target/arm/tcg/translate.c | 2 +-
target/avr/cpu.c | 25 +-
target/avr/translate.c | 2 +-
target/cris/cpu.c | 18 +-
target/cris/translate.c | 2 +-
target/hexagon/cpu.c | 23 +-
target/hexagon/translate.c | 5 +-
target/hppa/cpu.c | 57 ++++-
target/hppa/translate.c | 2 +-
target/i386/cpu.c | 21 ++
target/i386/tcg/sysemu/seg_helper.c | 23 ++
target/i386/tcg/tcg-cpu.c | 4 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu.c | 26 +-
target/loongarch/tcg/translate.c | 2 +-
target/m68k/cpu.c | 23 +-
target/m68k/translate.c | 4 +-
target/microblaze/cpu.c | 25 +-
target/microblaze/translate.c | 2 +-
target/mips/cpu.c | 16 +-
target/mips/tcg/translate.c | 14 +-
target/nios2/cpu.c | 20 +-
target/nios2/translate.c | 2 +-
target/openrisc/cpu.c | 24 +-
target/openrisc/translate.c | 2 +-
target/ppc/cpu.c | 9 +
target/ppc/cpu_init.c | 2 +-
target/ppc/helper_regs.c | 17 +-
target/ppc/translate.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
target/riscv/translate.c | 2 +-
target/rx/cpu.c | 16 +-
target/rx/translate.c | 2 +-
target/s390x/cpu.c | 55 ++++-
target/s390x/tcg/translate.c | 2 +-
target/sh4/cpu.c | 30 ++-
target/sh4/translate.c | 2 +-
target/sparc/cpu.c | 63 ++++-
target/sparc/translate.c | 2 +-
target/target-common.c | 10 +
target/tricore/cpu.c | 19 +-
target/tricore/translate.c | 2 +-
target/xtensa/cpu.c | 74 +++++-
target/xtensa/translate.c | 2 +-
{accel/tcg => tcg}/debuginfo.c | 3 +-
{accel/tcg => tcg}/perf.c | 14 +-
tcg/tcg.c | 2 +-
tests/tcg/multiarch/prot-none.c | 40 ++++
accel/tcg/meson.build | 16 +-
target/meson.build | 2 +
tcg/meson.build | 5 +
tests/guest-debug/run-test.py | 7 +-
tests/guest-debug/test_gdbstub.py | 56 +++++
tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 34 +--
tests/tcg/aarch64/gdbstub/test-sve.py | 33 +--
tests/tcg/multiarch/Makefile.target | 9 +-
tests/tcg/multiarch/gdbstub/interrupt.py | 47 +---
tests/tcg/multiarch/gdbstub/memory.py | 39 +--
tests/tcg/multiarch/gdbstub/prot-none.py | 22 ++
tests/tcg/multiarch/gdbstub/registers.py | 41 +---
tests/tcg/multiarch/gdbstub/sha1.py | 38 +--
.../multiarch/gdbstub/test-proc-mappings.py | 39 +--
.../multiarch/gdbstub/test-qxfer-auxv-read.py | 37 +--
.../gdbstub/test-thread-breakpoint.py | 37 +--
tests/tcg/s390x/gdbstub/test-signals-s390x.py | 42 +---
tests/tcg/s390x/gdbstub/test-svc.py | 39 +--
122 files changed, 1117 insertions(+), 1304 deletions(-)
create mode 100644 include/exec/vaddr.h
rename {accel => include}/tcg/debuginfo.h (96%)
rename {accel => include}/tcg/perf.h (95%)
create mode 100644 target/target-common.c
rename {accel/tcg => tcg}/debuginfo.c (98%)
rename {accel/tcg => tcg}/perf.c (97%)
create mode 100644 tests/tcg/multiarch/prot-none.c
create mode 100644 tests/guest-debug/test_gdbstub.py
create mode 100644 tests/tcg/multiarch/gdbstub/prot-none.py
--
2.34.1
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH 01/33] cpu-exec: simplify jump cache management
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 02/33] include/exec: Move vaddr defines to separate file Richard Henderson
` (33 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Alex Bennée
From: Paolo Bonzini <pbonzini@redhat.com>
Unless I'm missing something egregious, the jmp cache is only every
populated with a valid entry by the same thread that reads the cache.
Therefore, the contents of any valid entry are always consistent and
there is no need for any acquire/release magic.
Indeed ->tb has to be accessed with atomics, because concurrent
invalidations would otherwise cause data races. But ->pc is only ever
accessed by one thread, and accesses to ->tb and ->pc within tb_lookup
can never race with another tb_lookup. While the TranslationBlock
(especially the flags) could be modified by a concurrent invalidation,
store-release and load-acquire operations on the cache entry would
not add any additional ordering beyond what you get from performing
the accesses within a single thread.
Because of this, there is really nothing to win in splitting the CF_PCREL
and !CF_PCREL paths. It is easier to just always use the ->pc field in
the jump cache.
I noticed this while working on splitting commit 8ed558ec0cb
("accel/tcg: Introduce TARGET_TB_PCREL", 2022-10-04) into multiple
pieces, for the sake of finding a more fine-grained bisection
result for https://gitlab.com/qemu-project/qemu/-/issues/2092.
It does not (and does not intend to) fix that issue; therefore
it may make sense to not commit it until the root cause
of issue #2092 is found.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240122153409.351959-1-pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tb-jmp-cache.h | 8 +++--
accel/tcg/cpu-exec.c | 66 ++++++++++++++--------------------------
2 files changed, 28 insertions(+), 46 deletions(-)
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
index bb424c8a05..4ab8553afc 100644
--- a/accel/tcg/tb-jmp-cache.h
+++ b/accel/tcg/tb-jmp-cache.h
@@ -13,9 +13,11 @@
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
/*
- * Accessed in parallel; all accesses to 'tb' must be atomic.
- * For CF_PCREL, accesses to 'pc' must be protected by a
- * load_acquire/store_release to 'tb'.
+ * Invalidated in parallel; all accesses to 'tb' must be atomic.
+ * A valid entry is read/written by a single CPU, therefore there is
+ * no need for qatomic_rcu_read() and pc is always consistent with a
+ * non-NULL value of 'tb'. Strictly speaking pc is only needed for
+ * CF_PCREL, but it's used always for simplicity.
*/
struct CPUJumpCache {
struct rcu_head rcu;
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 67eda9865e..40c268bfa1 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -253,43 +253,29 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc,
hash = tb_jmp_cache_hash_func(pc);
jc = cpu->tb_jmp_cache;
- if (cflags & CF_PCREL) {
- /* Use acquire to ensure current load of pc from jc. */
- tb = qatomic_load_acquire(&jc->array[hash].tb);
-
- if (likely(tb &&
- jc->array[hash].pc == pc &&
- tb->cs_base == cs_base &&
- tb->flags == flags &&
- tb_cflags(tb) == cflags)) {
- return tb;
- }
- tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
- if (tb == NULL) {
- return NULL;
- }
- jc->array[hash].pc = pc;
- /* Ensure pc is written first. */
- qatomic_store_release(&jc->array[hash].tb, tb);
- } else {
- /* Use rcu_read to ensure current load of pc from *tb. */
- tb = qatomic_rcu_read(&jc->array[hash].tb);
-
- if (likely(tb &&
- tb->pc == pc &&
- tb->cs_base == cs_base &&
- tb->flags == flags &&
- tb_cflags(tb) == cflags)) {
- return tb;
- }
- tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
- if (tb == NULL) {
- return NULL;
- }
- /* Use the pc value already stored in tb->pc. */
- qatomic_set(&jc->array[hash].tb, tb);
+ tb = qatomic_read(&jc->array[hash].tb);
+ if (likely(tb &&
+ jc->array[hash].pc == pc &&
+ tb->cs_base == cs_base &&
+ tb->flags == flags &&
+ tb_cflags(tb) == cflags)) {
+ goto hit;
}
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
+ if (tb == NULL) {
+ return NULL;
+ }
+
+ jc->array[hash].pc = pc;
+ qatomic_set(&jc->array[hash].tb, tb);
+
+hit:
+ /*
+ * As long as tb is not NULL, the contents are consistent. Therefore,
+ * the virtual PC has to match for non-CF_PCREL translations.
+ */
+ assert((tb_cflags(tb) & CF_PCREL) || tb->pc == pc);
return tb;
}
@@ -1012,14 +998,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
*/
h = tb_jmp_cache_hash_func(pc);
jc = cpu->tb_jmp_cache;
- if (cflags & CF_PCREL) {
- jc->array[h].pc = pc;
- /* Ensure pc is written first. */
- qatomic_store_release(&jc->array[h].tb, tb);
- } else {
- /* Use the pc value already stored in tb->pc. */
- qatomic_set(&jc->array[h].tb, tb);
- }
+ jc->array[h].pc = pc;
+ qatomic_set(&jc->array[h].tb, tb);
}
#ifndef CONFIG_USER_ONLY
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 02/33] include/exec: Move vaddr defines to separate file
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
2024-01-28 4:41 ` [PATCH 01/33] cpu-exec: simplify jump cache management Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 03/33] hw/core: Include vaddr.h from cpu.h Richard Henderson
` (32 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Needed to work around circular includes. vaddr is currently defined in
cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need
cpu.h to know the size of the CPUState.
[Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to
sort out the circular inclusion.]
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-7-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[rth: Add include of vaddr.h into cpu-common.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-common.h | 13 +------------
include/exec/vaddr.h | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 12 deletions(-)
create mode 100644 include/exec/vaddr.h
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index fef3138d29..3109c6b67d 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -3,6 +3,7 @@
/* CPU interfaces that are target independent. */
+#include "exec/vaddr.h"
#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
#endif
@@ -14,18 +15,6 @@
#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
-/**
- * vaddr:
- * Type wide enough to contain any #target_ulong virtual address.
- */
-typedef uint64_t vaddr;
-#define VADDR_PRId PRId64
-#define VADDR_PRIu PRIu64
-#define VADDR_PRIo PRIo64
-#define VADDR_PRIx PRIx64
-#define VADDR_PRIX PRIX64
-#define VADDR_MAX UINT64_MAX
-
void cpu_exec_init_all(void);
void cpu_exec_step_atomic(CPUState *cpu);
diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h
new file mode 100644
index 0000000000..b9844afc77
--- /dev/null
+++ b/include/exec/vaddr.h
@@ -0,0 +1,18 @@
+/* Define vaddr. */
+
+#ifndef VADDR_H
+#define VADDR_H
+
+/**
+ * vaddr:
+ * Type wide enough to contain any #target_ulong virtual address.
+ */
+typedef uint64_t vaddr;
+#define VADDR_PRId PRId64
+#define VADDR_PRIu PRIu64
+#define VADDR_PRIo PRIo64
+#define VADDR_PRIx PRIx64
+#define VADDR_PRIX PRIX64
+#define VADDR_MAX UINT64_MAX
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 03/33] hw/core: Include vaddr.h from cpu.h
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
2024-01-28 4:41 ` [PATCH 01/33] cpu-exec: simplify jump cache management Richard Henderson
2024-01-28 4:41 ` [PATCH 02/33] include/exec: Move vaddr defines to separate file Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 04/33] target: Use vaddr in gen_intermediate_code Richard Henderson
` (31 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
cpu-common.h is only needed for vaddr
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-8-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 238c02c05e..db58f12233 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -22,8 +22,8 @@
#include "hw/qdev-core.h"
#include "disas/dis-asm.h"
-#include "exec/cpu-common.h"
#include "exec/hwaddr.h"
+#include "exec/vaddr.h"
#include "exec/memattrs.h"
#include "exec/tlb-common.h"
#include "qapi/qapi-types-run-state.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 04/33] target: Use vaddr in gen_intermediate_code
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (2 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 03/33] hw/core: Include vaddr.h from cpu.h Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses Richard Henderson
` (30 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Makes gen_intermediate_code() signature target agnostic so the function
can be called from accel/tcg/translate-all.c without target specifics.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-9-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/translator.h | 2 +-
target/alpha/translate.c | 2 +-
target/arm/tcg/translate.c | 2 +-
target/avr/translate.c | 2 +-
target/cris/translate.c | 2 +-
target/hexagon/translate.c | 2 +-
target/hppa/translate.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/tcg/translate.c | 2 +-
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/tcg/translate.c | 2 +-
target/nios2/translate.c | 2 +-
target/openrisc/translate.c | 2 +-
target/ppc/translate.c | 2 +-
target/riscv/translate.c | 2 +-
target/rx/translate.c | 2 +-
target/s390x/tcg/translate.c | 2 +-
target/sh4/translate.c | 2 +-
target/sparc/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/translate.c | 2 +-
22 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 6d3f59d095..b0412ea6b6 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -33,7 +33,7 @@
* the target-specific DisasContext, and then invoke translator_loop.
*/
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc);
+ vaddr pc, void *host_pc);
/**
* DisasJumpType:
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 32333081d8..134eb7225b 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b3660173d1..5fa8249723 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -9691,7 +9691,7 @@ static const TranslatorOps thumb_translator_ops = {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
diff --git a/target/avr/translate.c b/target/avr/translate.c
index cdffa04519..e5dd057799 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = { };
translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..ee1402a9a3 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 95579ae243..a14211cf68 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3ef39b1bd7..08d09d50d7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4631,7 +4631,7 @@ static const TranslatorOps hppa_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e193c74472..2808903661 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7088,7 +7088,7 @@ static const TranslatorOps i386_tr_ops = {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 21f4db6fbd..235515c629 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -343,7 +343,7 @@ static const TranslatorOps loongarch_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 4a0b0b2703..5ec88c5f0d 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6088,7 +6088,7 @@ static const TranslatorOps m68k_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 49bfb4a0ea..2e628647d1 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 13e43fa3b6..e10232738c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15554,7 +15554,7 @@ static const TranslatorOps mips_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index e806623594..3078372b36 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.base);
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index ecff4412b7..d4cbc5eaea 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 329da4d518..049f636927 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 071fbad7ef..ab18899122 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1287,7 +1287,7 @@ static const TranslatorOps riscv_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index c6ce717a95..2265bd14ac 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2266,7 +2266,7 @@ static const TranslatorOps rx_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 8df00b7df9..a5fd9cccaa 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6547,7 +6547,7 @@ static const TranslatorOps s390x_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 81f825f125..6a6d862b10 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2317,7 +2317,7 @@ static const TranslatorOps sh4_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 9387299559..97184fa403 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5327,7 +5327,7 @@ static const TranslatorOps sparc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 66553d1be0..f1156c39e7 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8472,7 +8472,7 @@ static const TranslatorOps tricore_tr_ops = {
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 87947236ca..e4772462b5 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1239,7 +1239,7 @@ static const TranslatorOps xtensa_translator_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
translator_loop(cpu, tb, max_insns, pc, host_pc,
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (3 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 04/33] target: Use vaddr in gen_intermediate_code Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 06/33] include/exec: typedef abi_ptr to vaddr Richard Henderson
` (29 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
DisasContextBase fields.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-10-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/translator.h | 6 +++---
target/mips/tcg/translate.h | 3 ++-
target/hexagon/translate.c | 3 ++-
target/m68k/translate.c | 2 +-
target/mips/tcg/translate.c | 12 ++++++------
5 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index b0412ea6b6..51624feb10 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -79,8 +79,8 @@ typedef enum DisasJumpType {
*/
typedef struct DisasContextBase {
TranslationBlock *tb;
- target_ulong pc_first;
- target_ulong pc_next;
+ vaddr pc_first;
+ vaddr pc_next;
DisasJumpType is_jmp;
int num_insns;
int max_insns;
@@ -235,7 +235,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc);
* Translators can use this to enforce the rule that only single-insn
* translation blocks are allowed to cross page boundaries.
*/
-static inline bool is_same_page(const DisasContextBase *db, target_ulong addr)
+static inline bool is_same_page(const DisasContextBase *db, vaddr addr)
{
return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
}
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index cffcfeab8c..93a78b8121 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -202,7 +202,8 @@ extern TCGv bcond;
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, \
- TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+ "%016" VADDR_PRIx \
+ ": %08x Invalid %s %03x %03x %03x\n", \
ctx->base.pc_next, ctx->opcode, op, \
ctx->opcode >> 26, ctx->opcode & 0x3F, \
((ctx->opcode >> 16) & 0x1F)); \
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index a14211cf68..f163eefe97 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
g_assert(ctx->base.num_insns == 1);
}
- HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
+ HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n",
+ ctx->base.pc_next);
HEX_DEBUG_LOG(" words = { ");
for (int i = 0; i < nwords; i++) {
HEX_DEBUG_LOG("0x%x, ", words[i]);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 5ec88c5f0d..f886190f88 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1457,7 +1457,7 @@ DISAS_INSN(undef)
* for the 680x0 series, as well as those that are implemented
* but actually illegal for CPU32 or pre-68020.
*/
- qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
+ qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\n",
insn, s->base.pc_next);
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index e10232738c..12094cc1e7 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
- TARGET_FMT_lx "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
goto out;
@@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
return;
@@ -11274,8 +11274,8 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 06/33] include/exec: typedef abi_ptr to vaddr
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (4 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 07/33] target: Uninline cpu_mmu_index() Richard Henderson
` (28 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-11-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu_ldst.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 6061e33ac9..eb8f3f0595 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
h2g_nocheck(x); \
})
#else
-typedef target_ulong abi_ptr;
-#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
+typedef vaddr abi_ptr;
+#define TARGET_ABI_FMT_ptr VADDR_PRIx
#endif
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 07/33] target: Uninline cpu_mmu_index()
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (5 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 06/33] include/exec: typedef abi_ptr to vaddr Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 16:41 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state() Richard Henderson
` (27 subsequent siblings)
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Uninlines the target-defined cpu_mmu_index() function by moving its
definition to target/*/cpu.c. This allows for compiling memory access
functions in accel/tcg/cputlb.c without having to know target specifics.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-13-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-common.h | 10 ++++++++++
target/alpha/cpu.h | 9 ---------
target/arm/cpu.h | 13 -------------
target/avr/cpu.h | 7 -------
target/cris/cpu.h | 4 ----
target/hexagon/cpu.h | 9 ---------
target/hppa/cpu.h | 13 -------------
target/i386/cpu.h | 7 -------
target/loongarch/cpu.h | 12 ------------
target/m68k/cpu.h | 4 ----
target/microblaze/cpu.h | 15 ---------------
target/mips/cpu.h | 5 -----
target/nios2/cpu.h | 6 ------
target/openrisc/cpu.h | 12 ------------
target/ppc/cpu.h | 8 --------
target/riscv/cpu.h | 3 ---
target/rx/cpu.h | 5 -----
target/s390x/cpu.h | 31 -------------------------------
target/sh4/cpu.h | 10 ----------
target/sparc/cpu.h | 28 ----------------------------
target/tricore/cpu.h | 5 -----
target/xtensa/cpu.h | 5 -----
target/alpha/cpu.c | 8 ++++++++
target/arm/cpu.c | 5 +++++
target/avr/cpu.c | 5 +++++
target/cris/cpu.c | 4 ++++
target/hexagon/cpu.c | 9 +++++++++
target/hppa/cpu.c | 13 +++++++++++++
target/i386/cpu.c | 7 +++++++
target/loongarch/cpu.c | 12 ++++++++++++
target/m68k/cpu.c | 5 +++++
target/microblaze/cpu.c | 16 ++++++++++++++++
target/mips/cpu.c | 5 +++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 12 ++++++++++++
target/ppc/cpu.c | 9 +++++++++
target/riscv/cpu_helper.c | 2 +-
target/rx/cpu.c | 5 +++++
target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++
target/sh4/cpu.c | 13 +++++++++++++
target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++
target/tricore/cpu.c | 5 +++++
target/xtensa/cpu.c | 4 ++++
43 files changed, 213 insertions(+), 212 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 3109c6b67d..4724135f30 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -34,6 +34,16 @@ void cpu_list_lock(void);
void cpu_list_unlock(void);
unsigned int cpu_list_generation_id_get(void);
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
+int cpu_mmu_index(CPUArchState *env, bool ifetch);
+
void tcg_iommu_init_notifier_list(CPUState *cpu);
void tcg_iommu_free_notifier_list(CPUState *cpu);
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index ce806587ca..abf778735a 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -389,15 +389,6 @@ enum {
#define TB_FLAG_UNALIGN (1u << 1)
-static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
-{
- int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
- if (env->flags & ENV_FLAG_PAL_MODE) {
- ret = MMU_KERNEL_IDX;
- }
- return ret;
-}
-
enum {
IR_V0 = 0,
IR_T0 = 1,
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ec276fcd57..b0edf2e540 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3268,19 +3268,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
-/**
- * cpu_mmu_index:
- * @env: The cpu environment
- * @ifetch: True for code access, false for data access.
- *
- * Return the core mmu index for the current translation regime.
- * This function is used by generic TCG code paths.
- */
-static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
-{
- return EX_TBFLAG_ANY(env->hflags, MMUIDX);
-}
-
/**
* sve_vq
* @env: the cpu context
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 7d5dd42575..d185d20dcb 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -184,13 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
env->features |= (1U << feature);
}
-#define cpu_mmu_index avr_cpu_mmu_index
-
-static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
-{
- return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
-}
-
void avr_cpu_tcg_init(void);
int cpu_avr_exec(CPUState *cpu);
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d830dcac5b..3904e5448c 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -260,10 +260,6 @@ enum {
/* MMU modes definitions */
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
-{
- return !!(env->pregs[PR_CCS] & U_FLAG);
-}
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 5c11ae3445..3eef58fe8f 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
*flags = hex_flags;
}
-static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
-#error System mode not supported on Hexagon yet
-#endif
-}
-
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 6a153405d2..7a181e8f33 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -281,19 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
}
-static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- if (env->psw & (ifetch ? PSW_C : PSW_D)) {
- return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
- }
- /* mmu disabled */
- return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
-#endif
-}
-
void hppa_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7f0786e8b9..6a5b180ccb 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define MMU_NESTED_IDX 3
#define MMU_PHYS_IDX 4
-static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
-{
- return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
- (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
- ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
-}
-
static inline int cpu_mmu_index_kernel(CPUX86State *env)
{
return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 0fa5e0ca93..64eac07a16 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -408,18 +408,6 @@ struct LoongArchCPUClass {
#define MMU_IDX_USER MMU_PLV_USER
#define MMU_IDX_DA 4
-static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_IDX_USER;
-#else
- if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
- return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
- }
- return MMU_IDX_DA;
-#endif
-}
-
static inline bool is_la64(CPULoongArchState *env)
{
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index d13427b0fe..aca4aa610b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -577,10 +577,6 @@ enum {
/* MMU modes definitions */
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
-{
- return (env->sr & SR_S) == 0 ? 1 : 0;
-}
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index b5374365f5..446af5dd4c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -434,21 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
-static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
-{
- MicroBlazeCPU *cpu = env_archcpu(env);
-
- /* Are we in nommu mode?. */
- if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
- return MMU_NOMMU_IDX;
- }
-
- if (env->msr & MSR_UM) {
- return MMU_USER_IDX;
- }
- return MMU_KERNEL_IDX;
-}
-
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1163a71f3c..4c9dc09a66 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1253,11 +1253,6 @@ static inline int hflags_mmu_index(uint32_t hflags)
}
}
-static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
-{
- return hflags_mmu_index(env->hflags);
-}
-
#include "exec/cpu-all.h"
/* Exceptions */
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2d79b5b298..4164a3432e 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env);
#define MMU_SUPERVISOR_IDX 0
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
-{
- return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
- MMU_SUPERVISOR_IDX;
-}
-
#ifndef CONFIG_USER_ONLY
hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b454014ddd..b1b7db5cbd 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -361,18 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
}
-static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
-{
- int ret = MMU_NOMMU_IDX; /* mmu is disabled */
-
- if (env->sr & (ifetch ? SR_IME : SR_DME)) {
- /* The mmu is enabled; test supervisor state. */
- ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
- }
-
- return ret;
-}
-
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
return (env->sr
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f8101ffa29..59587a8aba 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1624,14 +1624,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
/* MMU modes definitions */
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
-#endif
-}
/* Compatibility modes */
#if defined(TARGET_PPC64)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5f3955c38d..bca27278ed 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -498,7 +498,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
@@ -507,8 +506,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
-#define cpu_mmu_index riscv_cpu_mmu_index
-
#ifndef CONFIG_USER_ONLY
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 65f9cd2d0a..c53593d7aa 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
*flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
}
-static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
-{
- return 0;
-}
-
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
{
uint32_t psw = 0;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index fa3aac4f97..61c893b1b9 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -381,37 +381,6 @@ extern const VMStateDescription vmstate_s390_cpu;
#define MMU_HOME_IDX 2
#define MMU_REAL_IDX 3
-static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- if (!(env->psw.mask & PSW_MASK_DAT)) {
- return MMU_REAL_IDX;
- }
-
- if (ifetch) {
- if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
- return MMU_HOME_IDX;
- }
- return MMU_PRIMARY_IDX;
- }
-
- switch (env->psw.mask & PSW_MASK_ASC) {
- case PSW_ASC_PRIMARY:
- return MMU_PRIMARY_IDX;
- case PSW_ASC_SECONDARY:
- return MMU_SECONDARY_IDX;
- case PSW_ASC_HOME:
- return MMU_HOME_IDX;
- case PSW_ASC_ACCREG:
- /* Fallthrough: access register mode is not yet supported */
- default:
- abort();
- }
-#endif
-}
-
#ifdef CONFIG_TCG
#include "tcg/tcg_s390x.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 0e6fa65bae..9211da6bde 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env);
/* MMU modes definitions */
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
-{
- /* The instruction in a RTE delay slot is fetched in privileged
- mode, but executed in user mode. */
- if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
- return 0;
- } else {
- return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
- }
-}
#include "exec/cpu-all.h"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 12a11ecb26..51856152fa 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
}
#endif
-static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
-{
-#if defined(CONFIG_USER_ONLY)
- return MMU_USER_IDX;
-#elif !defined(TARGET_SPARC64)
- if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
- return MMU_PHYS_IDX;
- } else {
- return env->psrs;
- }
-#else
- /* IMMU or DMMU disabled. */
- if (ifetch
- ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
- : (env->lsu & DMMU_E) == 0) {
- return MMU_PHYS_IDX;
- } else if (cpu_hypervisor_mode(env)) {
- return MMU_PHYS_IDX;
- } else if (env->tl > 0) {
- return MMU_NUCLEUS_IDX;
- } else if (cpu_supervisor_mode(env)) {
- return MMU_KERNEL_IDX;
- } else {
- return MMU_USER_IDX;
- }
-#endif
-}
-
static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 2d4446cea5..220af69fc2 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env);
#define MMU_USER_IDX 2
-static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
-{
- return 0;
-}
-
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, PRIV, 0, 2)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 4b033ee924..6b8d0636d2 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
/* MMU modes definitions */
#define MMU_USER_IDX 3
-static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
-{
- return xtensa_get_cring(env);
-}
-
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b8ed29e343..ce18bedcca 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -25,6 +25,14 @@
#include "cpu.h"
#include "exec/exec-all.h"
+int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
+{
+ int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
+ if (env->flags & ENV_FLAG_PAL_MODE) {
+ ret = MMU_KERNEL_IDX;
+ }
+ return ret;
+}
static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
{
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 593695b424..0ee9a879f0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -49,6 +49,11 @@
#include "fpu/softfloat.h"
#include "cpregs.h"
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
+{
+ return EX_TBFLAG_ANY(env->hflags, MMUIDX);
+}
+
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index f5cbdc4a8c..ffb2234ecf 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -27,6 +27,11 @@
#include "tcg/debug-assert.h"
#include "hw/qdev-properties.h"
+int cpu_mmu_index(CPUAVRState *env, bool ifetch)
+{
+ return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
+}
+
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 9ba08e8b0c..1a8a544e31 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -27,6 +27,10 @@
#include "cpu.h"
#include "mmu.h"
+int cpu_mmu_index(CPUCRISState *env, bool ifetch)
+{
+ return !!(env->pregs[PR_CCS] & U_FLAG);
+}
static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index c0cd739e15..fd8dafad31 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -26,6 +26,15 @@
#include "tcg/tcg.h"
#include "exec/gdbstub.h"
+int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+#error System mode not supported on Hexagon yet
+#endif
+}
+
static void hexagon_v67_cpu_init(Object *obj) { }
static void hexagon_v68_cpu_init(Object *obj) { }
static void hexagon_v69_cpu_init(Object *obj) { }
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 14e17fa9aa..04f0b927b6 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -28,6 +28,19 @@
#include "fpu/softfloat.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ if (env->psw & (ifetch ? PSW_C : PSW_D)) {
+ return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
+ }
+ /* mmu disabled */
+ return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
+#endif
+}
+
static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
{
HPPACPU *cpu = HPPA_CPU(cs);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 03822d9ba8..d0adfb381b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -46,6 +46,13 @@
#include "disas/capstone.h"
#include "cpu-internal.h"
+int cpu_mmu_index(CPUX86State *env, bool ifetch)
+{
+ return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
+ (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
+ ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
+}
+
static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
/* Helpers for building CPUID[2] descriptors: */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 064540397d..316a85bacd 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -31,6 +31,18 @@
#include "tcg/tcg.h"
#endif
+int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_IDX_USER;
+#else
+ if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
+ return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ }
+ return MMU_IDX_DA;
+#endif
+}
+
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 1421e77c2c..604cdd5faf 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -24,6 +24,11 @@
#include "migration/vmstate.h"
#include "fpu/softfloat.h"
+int cpu_mmu_index(CPUM68KState *env, bool ifetch)
+{
+ return (env->sr & SR_S) == 0 ? 1 : 0;
+}
+
static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
{
M68kCPU *cpu = M68K_CPU(cs);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index bbb3335cad..f8891de41e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -32,6 +32,22 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUMBState *env, bool ifetch)
+{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
+ /* Are we in nommu mode?. */
+ if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
+ return MMU_NOMMU_IDX;
+ }
+
+ if (env->msr & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
+}
+
+
static const struct {
const char *name;
uint8_t version_id;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a0023edd43..34c0e40d32 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,6 +35,11 @@
#include "semihosting/semihost.h"
#include "fpu_helper.h"
+int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
+{
+ return hflags_mmu_index(env->hflags);
+}
+
const char regnames[32][3] = {
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index a27732bf2b..976b8c50ad 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -26,6 +26,12 @@
#include "gdbstub/helpers.h"
#include "hw/qdev-properties.h"
+int cpu_mmu_index(CPUNios2State *env, bool ifetch)
+{
+ return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
+ MMU_SUPERVISOR_IDX;
+}
+
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 381ebe00d3..fedeba3a3f 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -25,6 +25,18 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
+{
+ int ret = MMU_NOMMU_IDX; /* mmu is disabled */
+
+ if (env->sr & (ifetch ? SR_IME : SR_DME)) {
+ /* The mmu is enabled; test supervisor state. */
+ ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
+ }
+
+ return ret;
+}
+
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index e3ad8e0c27..53f1d5c370 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -27,6 +27,15 @@
#include "helper_regs.h"
#include "sysemu/tcg.h"
+int cpu_mmu_index(CPUPPCState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
+#endif
+}
+
target_ulong cpu_read_xer(const CPUPPCState *env)
{
if (is_isa300(env)) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c7cc7eb423..ea54081130 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -33,7 +33,7 @@
#include "debug.h"
#include "tcg/oversized-guest.h"
-int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
+int cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return 0;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index c5ffeffe32..b9f2bff9ce 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -26,6 +26,11 @@
#include "fpu/softfloat.h"
#include "tcg/debug-assert.h"
+int cpu_mmu_index(CPURXState *env, bool ifetch)
+{
+ return 0;
+}
+
static void rx_cpu_set_pc(CPUState *cs, vaddr value)
{
RXCPU *cpu = RX_CPU(cs);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 6acfa1c91b..bbb0b65bee 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -43,6 +43,37 @@
#define CR0_RESET 0xE0UL
#define CR14_RESET 0xC2000000UL;
+int cpu_mmu_index(CPUS390XState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ return MMU_REAL_IDX;
+ }
+
+ if (ifetch) {
+ if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
+ return MMU_HOME_IDX;
+ }
+ return MMU_PRIMARY_IDX;
+ }
+
+ switch (env->psw.mask & PSW_MASK_ASC) {
+ case PSW_ASC_PRIMARY:
+ return MMU_PRIMARY_IDX;
+ case PSW_ASC_SECONDARY:
+ return MMU_SECONDARY_IDX;
+ case PSW_ASC_HOME:
+ return MMU_HOME_IDX;
+ case PSW_ASC_ACCREG:
+ /* Fallthrough: access register mode is not yet supported */
+ default:
+ abort();
+ }
+#endif
+}
+
#ifndef CONFIG_USER_ONLY
static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
{
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 806a0ef875..e99fba7778 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -28,6 +28,19 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUSH4State *env, bool ifetch)
+{
+ /*
+ * The instruction in a RTE delay slot is fetched in privileged
+ * mode, but executed in user mode.
+ */
+ if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
+ return 0;
+ } else {
+ return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
+ }
+}
+
static void superh_cpu_set_pc(CPUState *cs, vaddr value)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index befa7fc4eb..e2b1feac2f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -29,6 +29,34 @@
//#define DEBUG_FEATURES
+int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
+{
+#if defined(CONFIG_USER_ONLY)
+ return MMU_USER_IDX;
+#elif !defined(TARGET_SPARC64)
+ if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
+ return MMU_PHYS_IDX;
+ } else {
+ return env->psrs;
+ }
+#else
+ /* IMMU or DMMU disabled. */
+ if (ifetch
+ ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
+ : (env->lsu & DMMU_E) == 0) {
+ return MMU_PHYS_IDX;
+ } else if (cpu_hypervisor_mode(env)) {
+ return MMU_PHYS_IDX;
+ } else if (env->tl > 0) {
+ return MMU_NUCLEUS_IDX;
+ } else if (cpu_supervisor_mode(env)) {
+ return MMU_KERNEL_IDX;
+ } else {
+ return MMU_USER_IDX;
+ }
+#endif
+}
+
static void sparc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(obj);
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 8acacdf0c0..a2bb1038ff 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -24,6 +24,11 @@
#include "qemu/error-report.h"
#include "tcg/debug-assert.h"
+int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
+{
+ return 0;
+}
+
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 99c0ca130f..7d69cef8cc 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -39,6 +39,10 @@
#include "exec/memory.h"
#endif
+int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
+{
+ return xtensa_get_cring(env);
+}
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state()
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (6 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 07/33] target: Uninline cpu_mmu_index() Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 09/33] include/exec: Move PAGE_* macros to common header Richard Henderson
` (26 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Required to compile accel/tcg/translate-all.c once for softmmu targets.
The function gets quite big for some targets so uninlining makes sense.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-14-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-common.h | 3 ++
target/alpha/cpu.h | 11 -------
target/arm/cpu.h | 3 --
target/avr/cpu.h | 18 -----------
target/cris/cpu.h | 10 ------
target/hexagon/cpu.h | 12 -------
target/hppa/cpu.h | 42 ------------------------
target/i386/cpu.h | 14 --------
target/loongarch/cpu.h | 12 -------
target/m68k/cpu.h | 16 ---------
target/microblaze/cpu.h | 8 -----
target/mips/cpu.h | 9 ------
target/nios2/cpu.h | 12 -------
target/openrisc/cpu.h | 10 ------
target/ppc/cpu.h | 13 --------
target/riscv/cpu.h | 3 --
target/rx/cpu.h | 9 ------
target/s390x/cpu.h | 24 --------------
target/sh4/cpu.h | 15 ---------
target/sparc/cpu.h | 33 -------------------
target/tricore/cpu.h | 12 -------
target/xtensa/cpu.h | 68 ---------------------------------------
target/alpha/cpu.c | 11 +++++++
target/avr/cpu.c | 18 +++++++++++
target/cris/cpu.c | 10 ++++++
target/hexagon/cpu.c | 12 +++++++
target/hppa/cpu.c | 42 ++++++++++++++++++++++++
target/i386/cpu.c | 14 ++++++++
target/loongarch/cpu.c | 12 +++++++
target/m68k/cpu.c | 16 +++++++++
target/microblaze/cpu.c | 7 ++++
target/mips/cpu.c | 9 ++++++
target/nios2/cpu.c | 12 +++++++
target/openrisc/cpu.c | 10 ++++++
target/ppc/helper_regs.c | 17 +++++-----
target/rx/cpu.c | 9 ++++++
target/s390x/cpu.c | 22 +++++++++++++
target/sh4/cpu.c | 15 +++++++++
target/sparc/cpu.c | 33 +++++++++++++++++++
target/tricore/cpu.c | 12 +++++++
target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++
41 files changed, 344 insertions(+), 362 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 4724135f30..1a8fad9222 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -44,6 +44,9 @@ unsigned int cpu_list_generation_id_get(void);
*/
int cpu_mmu_index(CPUArchState *env, bool ifetch);
+void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags);
+
void tcg_iommu_init_notifier_list(CPUState *cpu);
void tcg_iommu_free_notifier_list(CPUState *cpu);
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index abf778735a..2b0173577c 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -458,17 +458,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr);
#endif
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *pflags = env->flags & ENV_FLAG_TB_MASK;
-#ifdef CONFIG_USER_ONLY
- *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
#ifdef CONFIG_USER_ONLY
/* Copied from linux ieee_swcr_to_fpcr. */
static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b0edf2e540..a4ec37c8ed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3313,9 +3313,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
}
#endif
-void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags);
-
enum {
QEMU_PSCI_CONDUIT_DISABLED = 0,
QEMU_PSCI_CONDUIT_SMC = 1,
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d185d20dcb..284041a87a 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -193,24 +193,6 @@ enum {
TB_FLAGS_SKIP = 2,
};
-static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags = 0;
-
- *pc = env->pc_w * 2;
- *cs_base = 0;
-
- if (env->fullacc) {
- flags |= TB_FLAGS_FULL_ACCESS;
- }
- if (env->skip) {
- flags |= TB_FLAGS_SKIP;
- }
-
- *pflags = flags;
-}
-
static inline int cpu_interrupts_enabled(CPUAVRState *env)
{
return env->sregI != 0;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 3904e5448c..6df53f49c4 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -273,14 +273,4 @@ enum {
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = env->dslot |
- (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
- | X_FLAG | PFIX_FLAG));
-}
-
#endif
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 3eef58fe8f..1d42c33827 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -134,18 +134,6 @@ struct ArchCPU {
FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
-static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- uint32_t hex_flags = 0;
- *pc = env->gpr[HEX_REG_PC];
- *cs_base = 0;
- if (*pc == env->gpr[HEX_REG_SA0]) {
- hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
- }
- *flags = hex_flags;
-}
-
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7a181e8f33..b449ceea6b 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -314,48 +314,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
#define TB_FLAG_PRIV_SHIFT 8
#define TB_FLAG_UNALIGN 0x400
-static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags = env->psw_n * PSW_N;
-
- /* TB lookup assumes that PC contains the complete virtual address.
- If we leave space+offset separate, we'll get ITLB misses to an
- incomplete virtual address. This also means that we must separate
- out current cpu privilege from the low bits of IAOQ_F. */
-#ifdef CONFIG_USER_ONLY
- *pc = env->iaoq_f & -4;
- *cs_base = env->iaoq_b & -4;
- flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#else
- /* ??? E, T, H, L, B bits need to be here, when implemented. */
- flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
- flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
-
- *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
- env->iaoq_f & -4);
- *cs_base = env->iasq_f;
-
- /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
- low 32-bits of CS_BASE. This will succeed for all direct branches,
- which is the primary case we care about -- using goto_tb within a page.
- Failure is indicated by a zero difference. */
- if (env->iasq_f == env->iasq_b) {
- target_long diff = env->iaoq_b - env->iaoq_f;
- if (diff == (int32_t)diff) {
- *cs_base |= (uint32_t)diff;
- }
- }
- if ((env->sr[4] == env->sr[5])
- & (env->sr[4] == env->sr[6])
- & (env->sr[4] == env->sr[7])) {
- flags |= TB_FLAG_SR_SAME;
- }
-#endif
-
- *pflags = flags;
-}
-
target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6a5b180ccb..4352d0d163 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2315,20 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#include "hw/i386/apic.h"
#endif
-static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *flags = env->hflags |
- (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
- if (env->hflags & HF_CS64_MASK) {
- *cs_base = 0;
- *pc = env->eip;
- } else {
- *cs_base = env->segs[R_CS].base;
- *pc = (uint32_t)(*cs_base + env->eip);
- }
-}
-
void do_cpu_init(X86CPU *cpu);
#define MCE_INJECT_BROADCAST 1
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 64eac07a16..dd375d115f 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -443,18 +443,6 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
#define HW_FLAGS_VA32 0x20
#define HW_FLAGS_EUEN_ASXE 0x40
-static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
- *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
- *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
- *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
- *flags |= is_va32(env) * HW_FLAGS_VA32;
-}
-
#include "exec/cpu-all.h"
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index aca4aa610b..54dcfe1194 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -601,22 +601,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
#define TB_FLAGS_TRACE 16
#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
-static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
- if (env->sr & SR_S) {
- *flags |= TB_FLAGS_MSR_S;
- *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
- *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
- }
- if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
- *flags |= TB_FLAGS_TRACE;
- }
-}
-
void dump_mmu(CPUM68KState *env);
#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 446af5dd4c..27ccfc92b4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -415,14 +415,6 @@ void mb_tcg_init(void);
/* Ensure there is no overlap between the two masks. */
QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
-static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
- *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
-}
-
#if !defined(CONFIG_USER_ONLY)
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4c9dc09a66..05e9c902d1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1359,15 +1359,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu);
/* helper.c */
target_ulong exception_resume_pc(CPUMIPSState *env);
-static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->active_tc.PC;
- *cs_base = 0;
- *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
- MIPS_HFLAG_HWRENA_ULR);
-}
-
/**
* mips_cpu_create_with_clock:
* @typename: a MIPS CPU type.
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4164a3432e..d0616723fe 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -286,16 +286,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */
FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */
FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */
-static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
-
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
- | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
- | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
-}
-
#endif /* NIOS2_CPU_H */
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b1b7db5cbd..6997c7534e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -351,16 +351,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
env->shadow_gpr[0][i] = val;
}
-static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
- | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
- | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
-}
-
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
return (env->sr
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 59587a8aba..3bb10f0188 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2652,19 +2652,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer);
*/
#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
-#ifdef CONFIG_DEBUG_TCG
-void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags);
-#else
-static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->nip;
- *cs_base = 0;
- *flags = env->hflags;
-}
-#endif
-
G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
uintptr_t raddr);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bca27278ed..625ffc7622 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -688,9 +688,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
return cpu->cfg.vlen >> (sew + 3 - lmul);
}
-void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags);
-
void riscv_cpu_update_mask(CPURISCVState *env);
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index c53593d7aa..dcda762212 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -149,15 +149,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
#define RX_CPU_IRQ 0
#define RX_CPU_FIR 1
-static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
- *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
-}
-
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
{
uint32_t psw = 0;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 61c893b1b9..dd5b145539 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -382,31 +382,7 @@ extern const VMStateDescription vmstate_s390_cpu;
#define MMU_REAL_IDX 3
#ifdef CONFIG_TCG
-
#include "tcg/tcg_s390x.h"
-
-static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- if (env->psw.addr & 1) {
- /*
- * Instructions must be at even addresses.
- * This needs to be checked before address translation.
- */
- env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
- tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
- }
- *pc = env->psw.addr;
- *cs_base = env->ex_value;
- *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
- if (env->cregs[0] & CR0_AFP) {
- *flags |= FLAG_MASK_AFP;
- }
- if (env->cregs[0] & CR0_VECTOR) {
- *flags |= FLAG_MASK_VECTOR;
- }
-}
-
#endif /* CONFIG_TCG */
/* PER bits from control register 9 */
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9211da6bde..36aff035cf 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -370,19 +370,4 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}
-static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- /* For a gUSA region, notice the end of the region. */
- *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
- *flags = env->flags
- | (env->fpscr & TB_FLAG_FPSCR_MASK)
- | (env->sr & TB_FLAG_SR_MASK)
- | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
-#ifdef CONFIG_USER_ONLY
- *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
#endif /* SH4_CPU_H */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 51856152fa..60c72f06f5 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -749,39 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_HYPER (1 << 7)
#define TB_FLAG_ASI_SHIFT 24
-static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags;
- *pc = env->pc;
- *cs_base = env->npc;
- flags = cpu_mmu_index(env, false);
-#ifndef CONFIG_USER_ONLY
- if (cpu_supervisor_mode(env)) {
- flags |= TB_FLAG_SUPER;
- }
-#endif
-#ifdef TARGET_SPARC64
-#ifndef CONFIG_USER_ONLY
- if (cpu_hypervisor_mode(env)) {
- flags |= TB_FLAG_HYPER;
- }
-#endif
- if (env->pstate & PS_AM) {
- flags |= TB_FLAG_AM_ENABLED;
- }
- if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
- flags |= TB_FLAG_FPU_ENABLED;
- }
- flags |= env->asi << TB_FLAG_ASI_SHIFT;
-#else
- if (env->psref) {
- flags |= TB_FLAG_FPU_ENABLED;
- }
-#endif
- *pflags = flags;
-}
-
static inline bool tb_fpu_enabled(int tb_flags)
{
#if defined(CONFIG_USER_ONLY)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 220af69fc2..9537fef2b9 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -253,18 +253,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2)
void cpu_state_reset(CPUTriCoreState *s);
void tricore_tcg_init(void);
-static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- uint32_t new_flags = 0;
- *pc = env->PC;
- *cs_base = 0;
-
- new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
- extract32(env->PSW, 10, 2));
- *flags = new_flags;
-}
-
#define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
/* helpers.c */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 6b8d0636d2..2b6f2bdea7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -734,74 +734,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
- *flags |= xtensa_get_ring(env);
- if (env->sregs[PS] & PS_EXCM) {
- *flags |= XTENSA_TBFLAG_EXCM;
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
- target_ulong lend_dist =
- env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
-
- /*
- * 0 in the csbase_lend field means that there may not be a loopback
- * for any instruction that starts inside this page. Any other value
- * means that an instruction that ends at this offset from the page
- * start may loop back and will need loopback code to be generated.
- *
- * lend_dist is 0 when LEND points to the start of the page, but
- * no instruction that starts inside this page may end at offset 0,
- * so it's still correct.
- *
- * When an instruction ends at a page boundary it may only start in
- * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
- * for the TB that contains this instruction.
- */
- if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
- target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
-
- *cs_base = lend_dist;
- if (lbeg_off < 256) {
- *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
- }
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
- (env->sregs[LITBASE] & 1)) {
- *flags |= XTENSA_TBFLAG_LITBASE;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
- *flags |= XTENSA_TBFLAG_DEBUG;
- }
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
- *flags |= XTENSA_TBFLAG_ICOUNT;
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
- *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
- (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
- uint32_t windowstart = xtensa_replicate_windowstart(env) >>
- (env->sregs[WINDOW_BASE] + 1);
- uint32_t w = ctz32(windowstart | 0x8);
-
- *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
- *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
- PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
- } else {
- *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
- }
- if (env->yield_needed) {
- *flags |= XTENSA_TBFLAG_YIELD;
- }
-}
-
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
Clock *cpu_refclk);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index ce18bedcca..ce20a56270 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
return ret;
}
+void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *pflags = env->flags & ENV_FLAG_TB_MASK;
+#ifdef CONFIG_USER_ONLY
+ *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index ffb2234ecf..76dbe56284 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -32,6 +32,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch)
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
+void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags = 0;
+
+ *pc = env->pc_w * 2;
+ *cs_base = 0;
+
+ if (env->fullacc) {
+ flags |= TB_FLAGS_FULL_ACCESS;
+ }
+ if (env->skip) {
+ flags |= TB_FLAGS_SKIP;
+ }
+
+ *pflags = flags;
+}
+
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 1a8a544e31..6512ef8ee2 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch)
return !!(env->pregs[PR_CCS] & U_FLAG);
}
+void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->dslot |
+ (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
+ | X_FLAG | PFIX_FLAG));
+}
+
static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
CRISCPU *cpu = CRIS_CPU(cs);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index fd8dafad31..b2bbb21b59 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ uint32_t hex_flags = 0;
+ *pc = env->gpr[HEX_REG_PC];
+ *cs_base = 0;
+ if (*pc == env->gpr[HEX_REG_SA0]) {
+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
+ }
+ *flags = hex_flags;
+}
+
static void hexagon_v67_cpu_init(Object *obj) { }
static void hexagon_v68_cpu_init(Object *obj) { }
static void hexagon_v69_cpu_init(Object *obj) { }
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 04f0b927b6..2cc8e43b33 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -41,6 +41,48 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags = env->psw_n * PSW_N;
+
+ /* TB lookup assumes that PC contains the complete virtual address.
+ If we leave space+offset separate, we'll get ITLB misses to an
+ incomplete virtual address. This also means that we must separate
+ out current cpu privilege from the low bits of IAOQ_F. */
+#ifdef CONFIG_USER_ONLY
+ *pc = env->iaoq_f & -4;
+ *cs_base = env->iaoq_b & -4;
+ flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#else
+ /* ??? E, T, H, L, B bits need to be here, when implemented. */
+ flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
+ flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
+
+ *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
+ env->iaoq_f & -4);
+ *cs_base = env->iasq_f;
+
+ /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
+ low 32-bits of CS_BASE. This will succeed for all direct branches,
+ which is the primary case we care about -- using goto_tb within a page.
+ Failure is indicated by a zero difference. */
+ if (env->iasq_f == env->iasq_b) {
+ target_long diff = env->iaoq_b - env->iaoq_f;
+ if (diff == (int32_t)diff) {
+ *cs_base |= (uint32_t)diff;
+ }
+ }
+ if ((env->sr[4] == env->sr[5])
+ & (env->sr[4] == env->sr[6])
+ & (env->sr[4] == env->sr[7])) {
+ flags |= TB_FLAG_SR_SAME;
+ }
+#endif
+
+ *pflags = flags;
+}
+
static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
{
HPPACPU *cpu = HPPA_CPU(cs);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d0adfb381b..da32929558 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -53,6 +53,20 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch)
? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
}
+void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *flags = env->hflags |
+ (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
+ if (env->hflags & HF_CS64_MASK) {
+ *cs_base = 0;
+ *pc = env->eip;
+ } else {
+ *cs_base = env->segs[R_CS].base;
+ *pc = (uint32_t)(*cs_base + env->eip);
+ }
+}
+
static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
/* Helpers for building CPUID[2] descriptors: */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 316a85bacd..ea4281e177 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -43,6 +43,18 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
+ *flags |= is_va32(env) * HW_FLAGS_VA32;
+}
+
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 604cdd5faf..f9dc447897 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch)
return (env->sr & SR_S) == 0 ? 1 : 0;
}
+void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
+ if (env->sr & SR_S) {
+ *flags |= TB_FLAGS_MSR_S;
+ *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
+ *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
+ }
+ if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
+ *flags |= TB_FLAGS_TRACE;
+ }
+}
+
static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
{
M68kCPU *cpu = M68K_CPU(cs);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f8891de41e..4c270e941f 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch)
return MMU_KERNEL_IDX;
}
+void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
+ *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
+}
static const struct {
const char *name;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 34c0e40d32..4c3e1ec2d9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -40,6 +40,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
+void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->active_tc.PC;
+ *cs_base = 0;
+ *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
+ MIPS_HFLAG_HWRENA_ULR);
+}
+
const char regnames[32][3] = {
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 976b8c50ad..3e42889ce6 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch)
MMU_SUPERVISOR_IDX;
}
+void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
+ | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
+ | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
+}
+
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index fedeba3a3f..fda0dc9470 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
return ret;
}
+void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
+ | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
+ | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
+}
+
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index e0b2dcd02e..a506f9823c 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -217,26 +217,27 @@ void hreg_update_pmu_hflags(CPUPPCState *env)
env->hflags |= hreg_compute_pmu_hflags_value(env);
}
-#ifdef CONFIG_DEBUG_TCG
void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
+#ifdef CONFIG_DEBUG_TCG
+ uint32_t hflags_rebuilt = hreg_compute_hflags_value(env);
uint32_t hflags_current = env->hflags;
- uint32_t hflags_rebuilt;
- *pc = env->nip;
- *cs_base = 0;
- *flags = hflags_current;
-
- hflags_rebuilt = hreg_compute_hflags_value(env);
if (unlikely(hflags_current != hflags_rebuilt)) {
cpu_abort(env_cpu(env),
"TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
hflags_current, hflags_rebuilt);
}
-}
+ *flags = hflags_current;
+#else
+ *flags = env->hflags;
#endif
+ *pc = env->nip;
+ *cs_base = 0;
+}
+
void cpu_interrupt_exittb(CPUState *cs)
{
/*
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index b9f2bff9ce..de1cc7a5e6 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch)
return 0;
}
+void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
+ *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
+}
+
static void rx_cpu_set_pc(CPUState *cs, vaddr value)
{
RXCPU *cpu = RX_CPU(cs);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index bbb0b65bee..db1590472e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -74,6 +74,28 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ if (env->psw.addr & 1) {
+ /*
+ * Instructions must be at even addresses.
+ * This needs to be checked before address translation.
+ */
+ env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
+ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
+ }
+ *pc = env->psw.addr;
+ *cs_base = env->ex_value;
+ *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ if (env->cregs[0] & CR0_AFP) {
+ *flags |= FLAG_MASK_AFP;
+ }
+ if (env->cregs[0] & CR0_VECTOR) {
+ *flags |= FLAG_MASK_VECTOR;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
{
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index e99fba7778..eb7eb6f30a 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch)
}
}
+void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ /* For a gUSA region, notice the end of the region. */
+ *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
+ *flags = env->flags
+ | (env->fpscr & TB_FLAG_FPSCR_MASK)
+ | (env->sr & TB_FLAG_SR_MASK)
+ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+ *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
static void superh_cpu_set_pc(CPUState *cs, vaddr value)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index e2b1feac2f..99d57cc209 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -57,6 +57,39 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags;
+ *pc = env->pc;
+ *cs_base = env->npc;
+ flags = cpu_mmu_index(env, false);
+#ifndef CONFIG_USER_ONLY
+ if (cpu_supervisor_mode(env)) {
+ flags |= TB_FLAG_SUPER;
+ }
+#endif
+#ifdef TARGET_SPARC64
+#ifndef CONFIG_USER_ONLY
+ if (cpu_hypervisor_mode(env)) {
+ flags |= TB_FLAG_HYPER;
+ }
+#endif
+ if (env->pstate & PS_AM) {
+ flags |= TB_FLAG_AM_ENABLED;
+ }
+ if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
+ flags |= TB_FLAG_FPU_ENABLED;
+ }
+ flags |= env->asi << TB_FLAG_ASI_SHIFT;
+#else
+ if (env->psref) {
+ flags |= TB_FLAG_FPU_ENABLED;
+ }
+#endif
+ *pflags = flags;
+}
+
static void sparc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(obj);
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index a2bb1038ff..dff88184c9 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
+void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ uint32_t new_flags = 0;
+ *pc = env->PC;
+ *cs_base = 0;
+
+ new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
+ extract32(env->PSW, 10, 2));
+ *flags = new_flags;
+}
+
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7d69cef8cc..dfe0ff5c98 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
return xtensa_get_cring(env);
}
+void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+ *flags |= xtensa_get_ring(env);
+ if (env->sregs[PS] & PS_EXCM) {
+ *flags |= XTENSA_TBFLAG_EXCM;
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
+ target_ulong lend_dist =
+ env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
+
+ /*
+ * 0 in the csbase_lend field means that there may not be a loopback
+ * for any instruction that starts inside this page. Any other value
+ * means that an instruction that ends at this offset from the page
+ * start may loop back and will need loopback code to be generated.
+ *
+ * lend_dist is 0 when LEND points to the start of the page, but
+ * no instruction that starts inside this page may end at offset 0,
+ * so it's still correct.
+ *
+ * When an instruction ends at a page boundary it may only start in
+ * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
+ * for the TB that contains this instruction.
+ */
+ if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
+ target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
+
+ *cs_base = lend_dist;
+ if (lbeg_off < 256) {
+ *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
+ }
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ (env->sregs[LITBASE] & 1)) {
+ *flags |= XTENSA_TBFLAG_LITBASE;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ *flags |= XTENSA_TBFLAG_DEBUG;
+ }
+ if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ *flags |= XTENSA_TBFLAG_ICOUNT;
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+ *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
+ (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
+ uint32_t windowstart = xtensa_replicate_windowstart(env) >>
+ (env->sregs[WINDOW_BASE] + 1);
+ uint32_t w = ctz32(windowstart | 0x8);
+
+ *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+ *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+ PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
+ } else {
+ *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
+ }
+ if (env->yield_needed) {
+ *flags |= XTENSA_TBFLAG_YIELD;
+ }
+}
+
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 09/33] include/exec: Move PAGE_* macros to common header
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (7 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state() Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() " Richard Henderson
` (25 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
These don't vary across targets and are used in soon-to-be common code
(cputlb.c).
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-15-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 24 ------------------------
include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 5340907cfd..edee87d3f4 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -171,34 +171,10 @@ extern const TargetPageBits target_page;
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
-/* same as PROT_xxx */
-#define PAGE_READ 0x0001
-#define PAGE_WRITE 0x0002
-#define PAGE_EXEC 0x0004
-#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
-#define PAGE_VALID 0x0008
-/*
- * Original state of the write flag (used when tracking self-modifying code)
- */
-#define PAGE_WRITE_ORG 0x0010
-/*
- * Invalidate the TLB entry immediately, helpful for s390x
- * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
- */
-#define PAGE_WRITE_INV 0x0020
-/* For use with page_set_flags: page is being replaced; target_data cleared. */
-#define PAGE_RESET 0x0040
-/* For linux-user, indicates that the page is MAP_ANON. */
-#define PAGE_ANON 0x0080
-
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0100
#endif
-/* Target-specific bits that will be used via page_get_flags(). */
-#define PAGE_TARGET_1 0x0200
-#define PAGE_TARGET_2 0x0400
-
/*
* For linux-user, indicates that the page is mapped with the same semantics
* in both guest and host.
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 1a8fad9222..ba10351576 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -219,4 +219,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
G_NORETURN void cpu_loop_exit(CPUState *cpu);
G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
+/* same as PROT_xxx */
+#define PAGE_READ 0x0001
+#define PAGE_WRITE 0x0002
+#define PAGE_EXEC 0x0004
+#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
+#define PAGE_VALID 0x0008
+/*
+ * Original state of the write flag (used when tracking self-modifying code)
+ */
+#define PAGE_WRITE_ORG 0x0010
+/*
+ * Invalidate the TLB entry immediately, helpful for s390x
+ * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
+ */
+#define PAGE_WRITE_INV 0x0020
+/* For use with page_set_flags: page is being replaced; target_data cleared. */
+#define PAGE_RESET 0x0040
+/* For linux-user, indicates that the page is MAP_ANON. */
+#define PAGE_ANON 0x0080
+
+/* Target-specific bits that will be used via page_get_flags(). */
+#define PAGE_TARGET_1 0x0200
+#define PAGE_TARGET_2 0x0400
+
+/*
+ * For linux-user, indicates that the page is mapped with the same semantics
+ * in both guest and host.
+ */
+#define PAGE_PASSTHROUGH 0x0800
+
#endif /* CPU_COMMON_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() to common header
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (8 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 09/33] include/exec: Move PAGE_* macros to common header Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 16:29 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps Richard Henderson
` (24 subsequent siblings)
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Functions are target independent.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-17-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 25 -------------------------
include/exec/cpu-common.h | 26 ++++++++++++++++++++++++++
2 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index edee87d3f4..8501a33dbf 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -384,33 +384,8 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
#endif /* !CONFIG_USER_ONLY */
-/* accel/tcg/cpu-exec.c */
-int cpu_exec(CPUState *cpu);
-
/* Validate correct placement of CPUArchState. */
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
-/**
- * env_archcpu(env)
- * @env: The architecture environment
- *
- * Return the ArchCPU associated with the environment.
- */
-static inline ArchCPU *env_archcpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
-/**
- * env_cpu(env)
- * @env: The architecture environment
- *
- * Return the CPUState associated with the environment.
- */
-static inline CPUState *env_cpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
#endif /* CPU_ALL_H */
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index ba10351576..7e1a4afad8 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -7,6 +7,7 @@
#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
#endif
+#include "hw/core/cpu.h"
#define EXCP_INTERRUPT 0x10000 /* async interruption */
#define EXCP_HLT 0x10001 /* hlt instruction reached */
@@ -249,4 +250,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
*/
#define PAGE_PASSTHROUGH 0x0800
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+
+/**
+ * env_archcpu(env)
+ * @env: The architecture environment
+ *
+ * Return the ArchCPU associated with the environment.
+ */
+static inline ArchCPU *env_archcpu(CPUArchState *env)
+{
+ return (void *)env - sizeof(CPUState);
+}
+
+/**
+ * env_cpu(env)
+ * @env: The architecture environment
+ *
+ * Return the CPUState associated with the environment.
+ */
+static inline CPUState *env_cpu(CPUArchState *env)
+{
+ return (void *)env - sizeof(CPUState);
+}
+
#endif /* CPU_COMMON_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (9 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() " Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt Richard Henderson
` (23 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
The ifdef out of which it is moved is not quite right: do_interrupt is
only needed for system mode. Move it to the top of a different ifdef
block, which preserves its position within the structure for that case.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-18-anjo@rev.ng>
[rth: Split from a larger patch and simplified.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 479713a36e..d6fe55d471 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -58,11 +58,6 @@ struct TCGCPUOps {
* cpu execution loop (hack for x86 user mode).
*/
void (*fake_user_interrupt)(CPUState *cpu);
-#else
- /**
- * @do_interrupt: Callback for interrupt handling.
- */
- void (*do_interrupt)(CPUState *cpu);
#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
#ifdef CONFIG_USER_ONLY
/**
@@ -114,6 +109,8 @@ struct TCGCPUOps {
void (*record_sigbus)(CPUState *cpu, vaddr addr,
MMUAccessType access_type, uintptr_t ra);
#else
+ /** @do_interrupt: Callback for interrupt handling. */
+ void (*do_interrupt)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (10 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection Richard Henderson
` (22 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Anton Johansson
From: Anton Johansson <anjo@rev.ng>
Always include fake_user_interrupt in user-only build, despite
only being used for i386. This will enable cpu-exec.c to be
compiled only once.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20240119144024.14289-18-anjo@rev.ng>
[rth: Split out of a larger patch; remove TARGET_I386 conditional.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index d6fe55d471..3ed279836f 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -50,7 +50,7 @@ struct TCGCPUOps {
void (*debug_excp_handler)(CPUState *cpu);
#ifdef NEED_CPU_H
-#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
+#ifdef CONFIG_USER_ONLY
/**
* @fake_user_interrupt: Callback for 'fake exception' handling.
*
@@ -58,8 +58,7 @@ struct TCGCPUOps {
* cpu execution loop (hack for x86 user mode).
*/
void (*fake_user_interrupt)(CPUState *cpu);
-#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
-#ifdef CONFIG_USER_ONLY
+
/**
* record_sigsegv:
* @cpu: cpu context
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (11 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Richard Henderson
` (21 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich
From: Ilya Leoshkevich <iii@linux.ibm.com>
gdbserver ignores page protection by virtue of using /proc/$pid/mem.
Teach qemu gdbstub to do this too. This will not work if /proc is not
mounted; accept this limitation.
One alternative is to temporarily grant the missing PROT_* bit, but
this is inherently racy. Another alternative is self-debugging with
ptrace(POKE), which will break if QEMU itself is being debugged - a
much more severe limitation.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240109230808.583012-2-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
cpu-target.c | 76 +++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 61 insertions(+), 15 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index f6e07c3deb..c4e2169ab1 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -382,6 +382,9 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
vaddr l, page;
void * p;
uint8_t *buf = ptr;
+ ssize_t written;
+ int ret = -1;
+ int fd = -1;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
@@ -389,30 +392,73 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
if (l > len)
l = len;
flags = page_get_flags(page);
- if (!(flags & PAGE_VALID))
- return -1;
+ if (!(flags & PAGE_VALID)) {
+ goto out_close;
+ }
if (is_write) {
- if (!(flags & PAGE_WRITE))
- return -1;
+ if (flags & PAGE_WRITE) {
+ /* XXX: this code should not depend on lock_user */
+ p = lock_user(VERIFY_WRITE, addr, l, 0);
+ if (!p) {
+ goto out_close;
+ }
+ memcpy(p, buf, l);
+ unlock_user(p, addr, l);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_WRONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ /*
+ * If there is a TranslationBlock and we weren't bypassing the
+ * host page protection, the memcpy() above would SEGV,
+ * ultimately leading to page_unprotect(). So invalidate the
+ * translations manually. Both invalidation and pwrite() must
+ * be under mmap_lock() in order to prevent the creation of
+ * another TranslationBlock in between.
+ */
+ mmap_lock();
+ tb_invalidate_phys_range(addr, addr + l - 1);
+ written = pwrite(fd, buf, l, (off_t)g2h_untagged(addr));
+ mmap_unlock();
+ if (written != l) {
+ goto out_close;
+ }
+ }
+ } else if (flags & PAGE_READ) {
/* XXX: this code should not depend on lock_user */
- if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
- return -1;
- memcpy(p, buf, l);
- unlock_user(p, addr, l);
- } else {
- if (!(flags & PAGE_READ))
- return -1;
- /* XXX: this code should not depend on lock_user */
- if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
- return -1;
+ p = lock_user(VERIFY_READ, addr, l, 1);
+ if (!p) {
+ goto out_close;
+ }
memcpy(buf, p, l);
unlock_user(p, addr, 0);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_RDONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ if (pread(fd, buf, l, (off_t)g2h_untagged(addr)) != l) {
+ goto out_close;
+ }
}
len -= l;
buf += l;
addr += l;
}
- return 0;
+ ret = 0;
+out_close:
+ if (fd != -1) {
+ close(fd);
+ }
+out:
+ return ret;
}
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 14/33] tests/tcg: Factor out gdbstub test functions
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (12 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-29 9:38 ` Ilya Leoshkevich
2024-01-28 4:41 ` [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test Richard Henderson
` (20 subsequent siblings)
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich
From: Ilya Leoshkevich <iii@linux.ibm.com>
Both the report() function as well as the initial gdbstub test sequence
are copy-pasted into ~10 files with slight modifications. This
indicates that they are indeed generic, so factor them out. While
at it, add a few newlines to make the formatting closer to PEP-8.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20240109230808.583012-3-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/guest-debug/run-test.py | 7 ++-
tests/guest-debug/test_gdbstub.py | 56 +++++++++++++++++++
tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 34 +----------
tests/tcg/aarch64/gdbstub/test-sve.py | 33 +----------
tests/tcg/multiarch/gdbstub/interrupt.py | 47 ++--------------
tests/tcg/multiarch/gdbstub/memory.py | 39 +------------
tests/tcg/multiarch/gdbstub/registers.py | 41 ++------------
tests/tcg/multiarch/gdbstub/sha1.py | 38 ++-----------
.../multiarch/gdbstub/test-proc-mappings.py | 39 +------------
.../multiarch/gdbstub/test-qxfer-auxv-read.py | 37 +-----------
| 37 +-----------
tests/tcg/s390x/gdbstub/test-signals-s390x.py | 42 +-------------
tests/tcg/s390x/gdbstub/test-svc.py | 39 +------------
13 files changed, 94 insertions(+), 395 deletions(-)
create mode 100644 tests/guest-debug/test_gdbstub.py
diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py
index b13b27d4b1..368ff8a890 100755
--- a/tests/guest-debug/run-test.py
+++ b/tests/guest-debug/run-test.py
@@ -97,7 +97,12 @@ def log(output, msg):
sleep(1)
log(output, "GDB CMD: %s" % (gdb_cmd))
- result = subprocess.call(gdb_cmd, shell=True, stdout=output, stderr=stderr)
+ gdb_env = dict(os.environ)
+ gdb_pythonpath = gdb_env.get("PYTHONPATH", "").split(os.pathsep)
+ gdb_pythonpath.append(os.path.dirname(os.path.realpath(__file__)))
+ gdb_env["PYTHONPATH"] = os.pathsep.join(gdb_pythonpath)
+ result = subprocess.call(gdb_cmd, shell=True, stdout=output, stderr=stderr,
+ env=gdb_env)
# A result of greater than 128 indicates a fatal signal (likely a
# crash due to gdb internal failure). That's a problem for GDB and
diff --git a/tests/guest-debug/test_gdbstub.py b/tests/guest-debug/test_gdbstub.py
new file mode 100644
index 0000000000..1bc4ed131f
--- /dev/null
+++ b/tests/guest-debug/test_gdbstub.py
@@ -0,0 +1,56 @@
+"""Helper functions for gdbstub testing
+
+"""
+from __future__ import print_function
+import gdb
+import sys
+
+fail_count = 0
+
+
+def report(cond, msg):
+ """Report success/fail of a test"""
+ if cond:
+ print("PASS: {}".format(msg))
+ else:
+ print("FAIL: {}".format(msg))
+ global fail_count
+ fail_count += 1
+
+
+def main(test, expected_arch=None):
+ """Run a test function
+
+ This runs as the script it sourced (via -x, via run-test.py)."""
+ try:
+ inferior = gdb.selected_inferior()
+ arch = inferior.architecture()
+ print("ATTACHED: {}".format(arch))
+ if expected_arch is not None:
+ report(arch.name() == expected_arch,
+ "connected to {}".format(expected_arch))
+ except (gdb.error, AttributeError):
+ print("SKIP: not connected")
+ exit(0)
+
+ if gdb.parse_and_eval("$pc") == 0:
+ print("SKIP: PC not set")
+ exit(0)
+
+ try:
+ test()
+ except:
+ print("GDB Exception: {}".format(sys.exc_info()[0]))
+ global fail_count
+ fail_count += 1
+ import code
+ code.InteractiveConsole(locals=globals()).interact()
+ raise
+
+ try:
+ gdb.execute("kill")
+ except gdb.error:
+ pass
+
+ print("All tests complete: %d failures".format(fail_count))
+ exit(fail_count)
diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
index ee8d467e59..a78a3a2514 100644
--- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
+++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
@@ -8,19 +8,10 @@
#
import gdb
-import sys
+from test_gdbstub import main, report
initial_vlen = 0
-failcount = 0
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print ("PASS: %s" % (msg))
- else:
- print ("FAIL: %s" % (msg))
- global failcount
- failcount += 1
class TestBreakpoint(gdb.Breakpoint):
def __init__(self, sym_name="__sve_ld_done"):
@@ -64,26 +55,5 @@ def run_test():
gdb.execute("c")
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- report(arch.name() == "aarch64", "connected to aarch64")
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-try:
- # Run the actual tests
- run_test()
-except:
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- import code
- code.InteractiveConsole(locals=globals()).interact()
- raise
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test, expected_arch="aarch64")
diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py
index afd8ece98d..84cdcd4a32 100644
--- a/tests/tcg/aarch64/gdbstub/test-sve.py
+++ b/tests/tcg/aarch64/gdbstub/test-sve.py
@@ -6,20 +6,10 @@
#
import gdb
-import sys
+from test_gdbstub import main, report
MAGIC = 0xDEADBEEF
-failcount = 0
-
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print ("PASS: %s" % (msg))
- else:
- print ("FAIL: %s" % (msg))
- global failcount
- failcount += 1
def run_test():
"Run through the tests one by one"
@@ -54,24 +44,5 @@ def run_test():
report(str(v.type) == "uint64_t", "size of %s" % (reg))
report(int(v) == MAGIC, "%s is 0x%x" % (reg, MAGIC))
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- report(arch.name() == "aarch64", "connected to aarch64")
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-try:
- # Run the actual tests
- run_test()
-except:
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
-
-print("All tests complete: %d failures" % failcount)
-
-exit(failcount)
+main(run_test, expected_arch="aarch64")
diff --git a/tests/tcg/multiarch/gdbstub/interrupt.py b/tests/tcg/multiarch/gdbstub/interrupt.py
index c016e7afbb..90a45b5140 100644
--- a/tests/tcg/multiarch/gdbstub/interrupt.py
+++ b/tests/tcg/multiarch/gdbstub/interrupt.py
@@ -8,19 +8,7 @@
#
import gdb
-import sys
-
-failcount = 0
-
-
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print("PASS: %s" % (msg))
- else:
- print("FAIL: %s" % (msg))
- global failcount
- failcount += 1
+from test_gdbstub import main, report
def check_interrupt(thread):
@@ -59,6 +47,9 @@ def run_test():
Test if interrupting the code always lands us on the same thread when
running with scheduler-lock enabled.
"""
+ if len(gdb.selected_inferior().threads()) == 1:
+ print("SKIP: set to run on a single thread")
+ exit(0)
gdb.execute("set scheduler-locking on")
for thread in gdb.selected_inferior().threads():
@@ -66,32 +57,4 @@ def run_test():
"thread %d resumes correctly on interrupt" % thread.num)
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-if len(gdb.selected_inferior().threads()) == 1:
- print("SKIP: set to run on a single thread")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-# Finally kill the inferior and exit gdb with a count of failures
-gdb.execute("kill")
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gdbstub/memory.py
index fb1d06b7bb..532b92e7fb 100644
--- a/tests/tcg/multiarch/gdbstub/memory.py
+++ b/tests/tcg/multiarch/gdbstub/memory.py
@@ -9,18 +9,7 @@
import gdb
import sys
-
-failcount = 0
-
-
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print("PASS: %s" % (msg))
- else:
- print("FAIL: %s" % (msg))
- global failcount
- failcount += 1
+from test_gdbstub import main, report
def check_step():
@@ -99,29 +88,5 @@ def run_test():
report(cbp.hit_count == 0, "didn't reach backstop")
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-# Finally kill the inferior and exit gdb with a count of failures
-gdb.execute("kill")
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/multiarch/gdbstub/registers.py b/tests/tcg/multiarch/gdbstub/registers.py
index 688c061107..b3d13cb077 100644
--- a/tests/tcg/multiarch/gdbstub/registers.py
+++ b/tests/tcg/multiarch/gdbstub/registers.py
@@ -7,20 +7,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import gdb
-import sys
import xml.etree.ElementTree as ET
+from test_gdbstub import main, report
+
initial_vlen = 0
-failcount = 0
-
-def report(cond, msg):
- "Report success/fail of test."
- if cond:
- print("PASS: %s" % (msg))
- else:
- print("FAIL: %s" % (msg))
- global failcount
- failcount += 1
def fetch_xml_regmap():
@@ -75,6 +66,7 @@ def fetch_xml_regmap():
return reg_map
+
def get_register_by_regnum(reg_map, regnum):
"""
Helper to find a register from the map via its XML regnum
@@ -84,6 +76,7 @@ def get_register_by_regnum(reg_map, regnum):
return entry
return None
+
def crosscheck_remote_xml(reg_map):
"""
Cross-check the list of remote-registers with the XML info.
@@ -144,6 +137,7 @@ def crosscheck_remote_xml(reg_map):
elif "seen" not in x_reg:
print(f"{x_reg} wasn't seen in remote-registers")
+
def initial_register_read(reg_map):
"""
Do an initial read of all registers that we know gdb cares about
@@ -214,27 +208,4 @@ def run_test():
complete_and_diff(reg_map)
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- run_test()
-except (gdb.error):
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/multiarch/gdbstub/sha1.py b/tests/tcg/multiarch/gdbstub/sha1.py
index 416728415f..1ce711a402 100644
--- a/tests/tcg/multiarch/gdbstub/sha1.py
+++ b/tests/tcg/multiarch/gdbstub/sha1.py
@@ -7,19 +7,11 @@
#
import gdb
-import sys
+from test_gdbstub import main, report
+
initial_vlen = 0
-failcount = 0
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print("PASS: %s" % (msg))
- else:
- print("FAIL: %s" % (msg))
- global failcount
- failcount += 1
def check_break(sym_name):
"Setup breakpoint, continue and check we stopped."
@@ -35,6 +27,7 @@ def check_break(sym_name):
bp.delete()
+
def run_test():
"Run through the tests one by one"
@@ -57,28 +50,5 @@ def run_test():
# finally check we don't barf inspecting registers
gdb.execute("info registers")
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py
index 04ec61d219..564613fabf 100644
--- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py
+++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py
@@ -3,20 +3,7 @@
This runs as a sourced script (via -x, via run-test.py)."""
from __future__ import print_function
import gdb
-import sys
-
-
-n_failures = 0
-
-
-def report(cond, msg):
- """Report success/fail of a test"""
- if cond:
- print("PASS: {}".format(msg))
- else:
- print("FAIL: {}".format(msg))
- global n_failures
- n_failures += 1
+from test_gdbstub import main, report
def run_test():
@@ -37,26 +24,4 @@ def run_test():
# report("/sha1" in mappings, "Found the test binary name in the mappings")
-def main():
- """Prepare the environment and run through the tests"""
- try:
- inferior = gdb.selected_inferior()
- print("ATTACHED: {}".format(inferior.architecture().name()))
- except (gdb.error, AttributeError):
- print("SKIPPING (not connected)")
- exit(0)
-
- if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
- try:
- # Run the actual tests
- run_test()
- except gdb.error:
- report(False, "GDB Exception: {}".format(sys.exc_info()[0]))
- print("All tests complete: %d failures" % n_failures)
- exit(n_failures)
-
-
-main()
+main(run_test)
diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
index 926fa962b7..00c26ab4a9 100644
--- a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
+++ b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
@@ -6,18 +6,8 @@
#
import gdb
-import sys
+from test_gdbstub import main, report
-failcount = 0
-
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print ("PASS: %s" % (msg))
- else:
- print ("FAIL: %s" % (msg))
- global failcount
- failcount += 1
def run_test():
"Run through the tests one by one"
@@ -26,28 +16,5 @@ def run_test():
report(isinstance(auxv, str), "Fetched auxv from inferior")
report(auxv.find("sha1"), "Found test binary name in auxv")
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test)
--git a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
index e57d2a8db8..4d6b6b9fbe 100644
--- a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
+++ b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
@@ -6,18 +6,8 @@
#
import gdb
-import sys
+from test_gdbstub import main, report
-failcount = 0
-
-def report(cond, msg):
- "Report success/fail of test"
- if cond:
- print ("PASS: %s" % (msg))
- else:
- print ("FAIL: %s" % (msg))
- global failcount
- failcount += 1
def run_test():
"Run through the tests one by one"
@@ -29,28 +19,5 @@ def run_test():
frame = gdb.selected_frame()
report(str(frame.function()) == "thread1_func", "break @ %s"%frame)
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print ("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/s390x/gdbstub/test-signals-s390x.py b/tests/tcg/s390x/gdbstub/test-signals-s390x.py
index ca2bbc0b03..b6b7b39fc4 100644
--- a/tests/tcg/s390x/gdbstub/test-signals-s390x.py
+++ b/tests/tcg/s390x/gdbstub/test-signals-s390x.py
@@ -7,19 +7,7 @@
#
import gdb
-import sys
-
-failcount = 0
-
-
-def report(cond, msg):
- """Report success/fail of test"""
- if cond:
- print("PASS: %s" % (msg))
- else:
- print("FAIL: %s" % (msg))
- global failcount
- failcount += 1
+from test_gdbstub import main, report
def run_test():
@@ -42,31 +30,7 @@ def run_test():
gdb.Breakpoint("_exit")
gdb.execute("c")
status = int(gdb.parse_and_eval("$r2"))
- report(status == 0, "status == 0");
+ report(status == 0, "status == 0")
-#
-# This runs as the script it sourced (via -x, via run-test.py)
-#
-try:
- inferior = gdb.selected_inferior()
- arch = inferior.architecture()
- print("ATTACHED: %s" % arch.name())
-except (gdb.error, AttributeError):
- print("SKIPPING (not connected)", file=sys.stderr)
- exit(0)
-
-if gdb.parse_and_eval("$pc") == 0:
- print("SKIP: PC not set")
- exit(0)
-
-try:
- # Run the actual tests
- run_test()
-except (gdb.error):
- print("GDB Exception: %s" % (sys.exc_info()[0]))
- failcount += 1
- pass
-
-print("All tests complete: %d failures" % failcount)
-exit(failcount)
+main(run_test)
diff --git a/tests/tcg/s390x/gdbstub/test-svc.py b/tests/tcg/s390x/gdbstub/test-svc.py
index 804705fede..17210b4e02 100644
--- a/tests/tcg/s390x/gdbstub/test-svc.py
+++ b/tests/tcg/s390x/gdbstub/test-svc.py
@@ -3,20 +3,7 @@
This runs as a sourced script (via -x, via run-test.py)."""
from __future__ import print_function
import gdb
-import sys
-
-
-n_failures = 0
-
-
-def report(cond, msg):
- """Report success/fail of a test"""
- if cond:
- print("PASS: {}".format(msg))
- else:
- print("FAIL: {}".format(msg))
- global n_failures
- n_failures += 1
+from test_gdbstub import main, report
def run_test():
@@ -35,26 +22,4 @@ def run_test():
gdb.execute("si")
-def main():
- """Prepare the environment and run through the tests"""
- try:
- inferior = gdb.selected_inferior()
- print("ATTACHED: {}".format(inferior.architecture().name()))
- except (gdb.error, AttributeError):
- print("SKIPPING (not connected)")
- exit(0)
-
- if gdb.parse_and_eval('$pc') == 0:
- print("SKIP: PC not set")
- exit(0)
-
- try:
- # Run the actual tests
- run_test()
- except gdb.error:
- report(False, "GDB Exception: {}".format(sys.exc_info()[0]))
- print("All tests complete: %d failures" % n_failures)
- exit(n_failures)
-
-
-main()
+main(run_test)
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (13 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Richard Henderson
` (19 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich
From: Ilya Leoshkevich <iii@linux.ibm.com>
Make sure that qemu gdbstub, like gdbserver, allows reading from and
writing to PROT_NONE pages.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20240109230808.583012-4-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/multiarch/prot-none.c | 40 ++++++++++++++++++++++++
tests/tcg/multiarch/Makefile.target | 9 +++++-
tests/tcg/multiarch/gdbstub/prot-none.py | 22 +++++++++++++
3 files changed, 70 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/multiarch/prot-none.c
create mode 100644 tests/tcg/multiarch/gdbstub/prot-none.py
diff --git a/tests/tcg/multiarch/prot-none.c b/tests/tcg/multiarch/prot-none.c
new file mode 100644
index 0000000000..dc56aadb3c
--- /dev/null
+++ b/tests/tcg/multiarch/prot-none.c
@@ -0,0 +1,40 @@
+/*
+ * Test that GDB can access PROT_NONE pages.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include <assert.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+
+void break_here(void *q)
+{
+}
+
+int main(void)
+{
+ long pagesize = sysconf(_SC_PAGESIZE);
+ void *p, *q;
+ int err;
+
+ p = mmap(NULL, pagesize * 2, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ assert(p != MAP_FAILED);
+ q = p + pagesize - 1;
+ strcpy(q, "42");
+
+ err = mprotect(p, pagesize * 2, PROT_NONE);
+ assert(err == 0);
+
+ break_here(q);
+
+ err = mprotect(p, pagesize * 2, PROT_READ);
+ assert(err == 0);
+ if (getenv("PROT_NONE_PY")) {
+ assert(strcmp(q, "24") == 0);
+ }
+
+ return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/multiarch/Makefile.target b/tests/tcg/multiarch/Makefile.target
index d31ba8d6ae..315a2e1358 100644
--- a/tests/tcg/multiarch/Makefile.target
+++ b/tests/tcg/multiarch/Makefile.target
@@ -101,13 +101,20 @@ run-gdbstub-registers: sha512
--bin $< --test $(MULTIARCH_SRC)/gdbstub/registers.py, \
checking register enumeration)
+run-gdbstub-prot-none: prot-none
+ $(call run-test, $@, env PROT_NONE_PY=1 $(GDB_SCRIPT) \
+ --gdb $(GDB) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(MULTIARCH_SRC)/gdbstub/prot-none.py, \
+ accessing PROT_NONE memory)
+
else
run-gdbstub-%:
$(call skip-test, "gdbstub test $*", "need working gdb with $(patsubst -%,,$(TARGET_NAME)) support")
endif
EXTRA_RUNS += run-gdbstub-sha1 run-gdbstub-qxfer-auxv-read \
run-gdbstub-proc-mappings run-gdbstub-thread-breakpoint \
- run-gdbstub-registers
+ run-gdbstub-registers run-gdbstub-prot-none
# ARM Compatible Semi Hosting Tests
#
diff --git a/tests/tcg/multiarch/gdbstub/prot-none.py b/tests/tcg/multiarch/gdbstub/prot-none.py
new file mode 100644
index 0000000000..f1f1dd82cb
--- /dev/null
+++ b/tests/tcg/multiarch/gdbstub/prot-none.py
@@ -0,0 +1,22 @@
+"""Test that GDB can access PROT_NONE pages.
+
+This runs as a sourced script (via -x, via run-test.py).
+
+SPDX-License-Identifier: GPL-2.0-or-later
+"""
+from test_gdbstub import main, report
+
+
+def run_test():
+ """Run through the tests one by one"""
+ gdb.Breakpoint("break_here")
+ gdb.execute("continue")
+ val = gdb.parse_and_eval("*(char[2] *)q").string()
+ report(val == "42", "{} == 42".format(val))
+ gdb.execute("set *(char[3] *)q = \"24\"")
+ gdb.execute("continue")
+ exitcode = int(gdb.parse_and_eval("$_exitcode"))
+ report(exitcode == 0, "{} == 0".format(exitcode))
+
+
+main(run_test)
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (14 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 16:27 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user Richard Henderson
` (18 subsequent siblings)
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Replace the manual rcu_read_(un)lock calls in cpu_exec().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240124074201.8239-2-philmd@linaro.org>
[rth: Use RCU_READ_LOCK_GUARD not WITH_RCU_READ_LOCK_GUARD]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 40c268bfa1..950dad63cb 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -1050,7 +1050,7 @@ int cpu_exec(CPUState *cpu)
return EXCP_HALTED;
}
- rcu_read_lock();
+ RCU_READ_LOCK_GUARD();
cpu_exec_enter(cpu);
/*
@@ -1064,8 +1064,6 @@ int cpu_exec(CPUState *cpu)
ret = cpu_exec_setjmp(cpu, &sc);
cpu_exec_exit(cpu);
- rcu_read_unlock();
-
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (15 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c Richard Henderson
` (17 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich, Philippe Mathieu-Daudé
From: Ilya Leoshkevich <iii@linux.ibm.com>
Currently qemu_target_page_mask() is usable only from the softmmu
code. Make it possible to use it from the *-user code as well.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20231208003754.3688038-2-iii@linux.ibm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240124075609.14756-2-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[rth: Split out change to accel/tcg/perf.c]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
system/physmem.c | 5 -----
target/target-common.c | 10 ++++++++++
target/meson.build | 2 ++
3 files changed, 12 insertions(+), 5 deletions(-)
create mode 100644 target/target-common.c
diff --git a/system/physmem.c b/system/physmem.c
index cc68a79763..5e66d9ae36 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -3431,11 +3431,6 @@ size_t qemu_target_page_size(void)
return TARGET_PAGE_SIZE;
}
-int qemu_target_page_mask(void)
-{
- return TARGET_PAGE_MASK;
-}
-
int qemu_target_page_bits(void)
{
return TARGET_PAGE_BITS;
diff --git a/target/target-common.c b/target/target-common.c
new file mode 100644
index 0000000000..903b10cfe4
--- /dev/null
+++ b/target/target-common.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "exec/target_page.h"
+
+int qemu_target_page_mask(void)
+{
+ return TARGET_PAGE_MASK;
+}
diff --git a/target/meson.build b/target/meson.build
index a53a60486f..dee2ac47e0 100644
--- a/target/meson.build
+++ b/target/meson.build
@@ -19,3 +19,5 @@ subdir('sh4')
subdir('sparc')
subdir('tricore')
subdir('xtensa')
+
+specific_ss.add(files('target-common.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (16 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:41 ` [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code Richard Henderson
` (16 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel
Cc: Ilya Leoshkevich, Alex Bennée, Philippe Mathieu-Daudé
From: Ilya Leoshkevich <iii@linux.ibm.com>
Stop using TARGET_PAGE_MASK in order to make perf.c more
target-agnostic.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231212003837.64090-2-iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240125054631.78867-2-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
index cd1aa99a7e..ba75c1bbe4 100644
--- a/accel/tcg/perf.c
+++ b/accel/tcg/perf.c
@@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "elf.h"
+#include "exec/target_page.h"
#include "exec/exec-all.h"
#include "qemu/timer.h"
#include "tcg/tcg.h"
@@ -335,7 +336,7 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb,
/* FIXME: This replicates the restore_state_to_opc() logic. */
q[insn].address = gen_insn_data[insn * start_words + 0];
if (tb_cflags(tb) & CF_PCREL) {
- q[insn].address |= (guest_pc & TARGET_PAGE_MASK);
+ q[insn].address |= (guest_pc & qemu_target_page_mask());
} else {
#if defined(TARGET_I386)
q[insn].address -= tb->cs_base;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (17 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c Richard Henderson
@ 2024-01-28 4:41 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c Richard Henderson
` (15 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich, Philippe Mathieu-Daudé
From: Ilya Leoshkevich <iii@linux.ibm.com>
Currently tb_cflags() is defined in exec-all.h, which is not usable
from target-agnostic code. Move it to translation-block.h, which is.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231212003837.64090-3-iii@linux.ibm.com>
Message-Id: <20240125054631.78867-3-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 6 ------
include/exec/translation-block.h | 6 ++++++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index df3d93a2e2..ce36bb10d4 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -459,12 +459,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size,
#endif
-/* Hide the qatomic_read to make code a little easier on the eyes */
-static inline uint32_t tb_cflags(const TranslationBlock *tb)
-{
- return qatomic_read(&tb->cflags);
-}
-
static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
{
#ifdef CONFIG_USER_ONLY
diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
index e2b26e16da..48211c890a 100644
--- a/include/exec/translation-block.h
+++ b/include/exec/translation-block.h
@@ -145,4 +145,10 @@ struct TranslationBlock {
/* The alignment given to TranslationBlock during allocation. */
#define CODE_GEN_ALIGN 16
+/* Hide the qatomic_read to make code a little easier on the eyes */
+static inline uint32_t tb_cflags(const TranslationBlock *tb)
+{
+ return qatomic_read(&tb->cflags);
+}
+
#endif /* EXEC_TRANSLATION_BLOCK_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (18 preceding siblings ...)
2024-01-28 4:41 ` [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/ Richard Henderson
` (14 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich, Alex Bennée
From: Ilya Leoshkevich <iii@linux.ibm.com>
Preparation for moving perf.c to tcg/.
This affects only profiling guest code, which has code in a non-0 based
segment, e.g., 16-bit code, which is not particularly important.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231212003837.64090-4-iii@linux.ibm.com>
Message-Id: <20240125054631.78867-4-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/perf.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
index ba75c1bbe4..68a46b1b52 100644
--- a/accel/tcg/perf.c
+++ b/accel/tcg/perf.c
@@ -337,10 +337,6 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb,
q[insn].address = gen_insn_data[insn * start_words + 0];
if (tb_cflags(tb) & CF_PCREL) {
q[insn].address |= (guest_pc & qemu_target_page_mask());
- } else {
-#if defined(TARGET_I386)
- q[insn].address -= tb->cs_base;
-#endif
}
q[insn].flags = DEBUGINFO_SYMBOL | (jitdump ? DEBUGINFO_LINE : 0);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (19 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson Richard Henderson
` (13 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Ilya Leoshkevich, Philippe Mathieu-Daudé
From: Ilya Leoshkevich <iii@linux.ibm.com>
tcg/ should not depend on accel/tcg/, but perf and debuginfo
support provided by the latter are being used by tcg/tcg.c.
Since that's the only user, move both to tcg/.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231212003837.64090-5-iii@linux.ibm.com>
Message-Id: <20240125054631.78867-5-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
{accel => include}/tcg/debuginfo.h | 4 ++--
{accel => include}/tcg/perf.h | 4 ++--
accel/tcg/translate-all.c | 2 +-
hw/core/loader.c | 2 +-
linux-user/elfload.c | 2 +-
linux-user/exit.c | 2 +-
linux-user/main.c | 2 +-
system/vl.c | 2 +-
{accel/tcg => tcg}/debuginfo.c | 3 +--
{accel/tcg => tcg}/perf.c | 7 +++----
tcg/tcg.c | 2 +-
accel/tcg/meson.build | 4 ----
tcg/meson.build | 5 +++++
13 files changed, 20 insertions(+), 21 deletions(-)
rename {accel => include}/tcg/debuginfo.h (96%)
rename {accel => include}/tcg/perf.h (95%)
rename {accel/tcg => tcg}/debuginfo.c (98%)
rename {accel/tcg => tcg}/perf.c (99%)
diff --git a/accel/tcg/debuginfo.h b/include/tcg/debuginfo.h
similarity index 96%
rename from accel/tcg/debuginfo.h
rename to include/tcg/debuginfo.h
index f064e1c144..858535b5da 100644
--- a/accel/tcg/debuginfo.h
+++ b/include/tcg/debuginfo.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
-#ifndef ACCEL_TCG_DEBUGINFO_H
-#define ACCEL_TCG_DEBUGINFO_H
+#ifndef TCG_DEBUGINFO_H
+#define TCG_DEBUGINFO_H
#include "qemu/bitops.h"
diff --git a/accel/tcg/perf.h b/include/tcg/perf.h
similarity index 95%
rename from accel/tcg/perf.h
rename to include/tcg/perf.h
index f92dd52c69..c96b5920a3 100644
--- a/accel/tcg/perf.h
+++ b/include/tcg/perf.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
-#ifndef ACCEL_TCG_PERF_H
-#define ACCEL_TCG_PERF_H
+#ifndef TCG_PERF_H
+#define TCG_PERF_H
#if defined(CONFIG_TCG) && defined(CONFIG_LINUX)
/* Start writing perf-<pid>.map. */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 1737bb3da5..1c695efe02 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -63,7 +63,7 @@
#include "tb-context.h"
#include "internal-common.h"
#include "internal-target.h"
-#include "perf.h"
+#include "tcg/perf.h"
#include "tcg/insn-start-words.h"
TBContext tb_ctx;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index e7a9b3775b..b8e52f3fb0 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -62,7 +62,7 @@
#include "hw/boards.h"
#include "qemu/cutils.h"
#include "sysemu/runstate.h"
-#include "accel/tcg/debuginfo.h"
+#include "tcg/debuginfo.h"
#include <zlib.h>
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index daf7ef8435..b8eef893d0 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -22,7 +22,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "target_signal.h"
-#include "accel/tcg/debuginfo.h"
+#include "tcg/debuginfo.h"
#ifdef TARGET_ARM
#include "target/arm/cpu-features.h"
diff --git a/linux-user/exit.c b/linux-user/exit.c
index 50266314e0..1ff8fe4f07 100644
--- a/linux-user/exit.c
+++ b/linux-user/exit.c
@@ -17,7 +17,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
-#include "accel/tcg/perf.h"
+#include "tcg/perf.h"
#include "gdbstub/syscalls.h"
#include "qemu.h"
#include "user-internals.h"
diff --git a/linux-user/main.c b/linux-user/main.c
index c9470eeccf..74b2fbb393 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -54,7 +54,7 @@
#include "signal-common.h"
#include "loader.h"
#include "user-mmap.h"
-#include "accel/tcg/perf.h"
+#include "tcg/perf.h"
#ifdef CONFIG_SEMIHOSTING
#include "semihosting/semihost.h"
diff --git a/system/vl.c b/system/vl.c
index 788d88ea03..60fd1e56b6 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -96,7 +96,7 @@
#endif
#include "sysemu/qtest.h"
#ifdef CONFIG_TCG
-#include "accel/tcg/perf.h"
+#include "tcg/perf.h"
#endif
#include "disas/disas.h"
diff --git a/accel/tcg/debuginfo.c b/tcg/debuginfo.c
similarity index 98%
rename from accel/tcg/debuginfo.c
rename to tcg/debuginfo.c
index 71c66d04d1..3753f7ef67 100644
--- a/accel/tcg/debuginfo.c
+++ b/tcg/debuginfo.c
@@ -6,11 +6,10 @@
#include "qemu/osdep.h"
#include "qemu/lockable.h"
+#include "tcg/debuginfo.h"
#include <elfutils/libdwfl.h>
-#include "debuginfo.h"
-
static QemuMutex lock;
static Dwfl *dwfl;
static const Dwfl_Callbacks dwfl_callbacks = {
diff --git a/accel/tcg/perf.c b/tcg/perf.c
similarity index 99%
rename from accel/tcg/perf.c
rename to tcg/perf.c
index 68a46b1b52..412a987d95 100644
--- a/accel/tcg/perf.c
+++ b/tcg/perf.c
@@ -11,13 +11,12 @@
#include "qemu/osdep.h"
#include "elf.h"
#include "exec/target_page.h"
-#include "exec/exec-all.h"
+#include "exec/translation-block.h"
#include "qemu/timer.h"
+#include "tcg/debuginfo.h"
+#include "tcg/perf.h"
#include "tcg/tcg.h"
-#include "debuginfo.h"
-#include "perf.h"
-
static FILE *safe_fopen_w(const char *path)
{
int saved_errno;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e2c38f6d11..eeff4c1d51 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -55,7 +55,7 @@
#include "tcg/tcg-ldst.h"
#include "tcg/tcg-temp-internal.h"
#include "tcg-internal.h"
-#include "accel/tcg/perf.h"
+#include "tcg/perf.h"
#ifdef CONFIG_USER_ONLY
#include "exec/user/guest-base.h"
#endif
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index c15ac9ac8f..46f7d53eeb 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -16,10 +16,6 @@ tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
if get_option('plugins')
tcg_ss.add(files('plugin-gen.c'))
endif
-tcg_ss.add(when: libdw, if_true: files('debuginfo.c'))
-if host_os == 'linux'
- tcg_ss.add(files('perf.c'))
-endif
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
diff --git a/tcg/meson.build b/tcg/meson.build
index 5afdec1e1a..8251589fd4 100644
--- a/tcg/meson.build
+++ b/tcg/meson.build
@@ -22,6 +22,11 @@ if get_option('tcg_interpreter')
tcg_ss.add(files('tci.c'))
endif
+tcg_ss.add(when: libdw, if_true: files('debuginfo.c'))
+if host_os == 'linux'
+ tcg_ss.add(files('perf.c'))
+endif
+
tcg_ss = tcg_ss.apply({})
libtcg_user = static_library('tcg_user',
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (20 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/ Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() Richard Henderson
` (12 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
tcg_ss[] source set contains target-specific units.
Rename it as 'tcg_specific_ss[]' for clarity.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240124101639.30056-2-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/meson.build | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 46f7d53eeb..aef80de967 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,8 +1,8 @@
-tcg_ss = ss.source_set()
common_ss.add(when: 'CONFIG_TCG', if_true: files(
'cpu-exec-common.c',
))
-tcg_ss.add(files(
+tcg_specific_ss = ss.source_set()
+tcg_specific_ss.add(files(
'tcg-all.c',
'cpu-exec.c',
'tb-maint.c',
@@ -11,12 +11,12 @@ tcg_ss.add(files(
'translate-all.c',
'translator.c',
))
-tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
-tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
+tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
+tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
if get_option('plugins')
- tcg_ss.add(files('plugin-gen.c'))
+ tcg_specific_ss.add(files('plugin-gen.c'))
endif
-specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
+specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy()
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (21 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() Richard Henderson
` (11 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
tcg_cpus_destroy() operates on a single vCPU, rename it
as 'tcg_cpu_destroy'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240124101639.30056-3-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-accel-ops.h | 2 +-
accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
accel/tcg/tcg-accel-ops-rr.c | 2 +-
accel/tcg/tcg-accel-ops.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
index f9bc6330e2..17c7ed00eb 100644
--- a/accel/tcg/tcg-accel-ops.h
+++ b/accel/tcg/tcg-accel-ops.h
@@ -14,7 +14,7 @@
#include "sysemu/cpus.h"
-void tcg_cpus_destroy(CPUState *cpu);
+void tcg_cpu_destroy(CPUState *cpu);
int tcg_cpus_exec(CPUState *cpu);
void tcg_handle_interrupt(CPUState *cpu, int mask);
void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
index af7307013a..bcba314a65 100644
--- a/accel/tcg/tcg-accel-ops-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -118,7 +118,7 @@ static void *mttcg_cpu_thread_fn(void *arg)
qemu_wait_io_event(cpu);
} while (!cpu->unplug || cpu_can_run(cpu));
- tcg_cpus_destroy(cpu);
+ tcg_cpu_destroy(cpu);
bql_unlock();
rcu_remove_force_rcu_notifier(&force_rcu.notifier);
rcu_unregister_thread();
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
index 3208035d85..0617f66b5b 100644
--- a/accel/tcg/tcg-accel-ops-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -131,7 +131,7 @@ static void rr_deal_with_unplugged_cpus(void)
CPU_FOREACH(cpu) {
if (cpu->unplug && !cpu_can_run(cpu)) {
- tcg_cpus_destroy(cpu);
+ tcg_cpu_destroy(cpu);
break;
}
}
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 813065c0ec..9b84b84218 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -63,7 +63,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
cpu->tcg_cflags |= cflags;
}
-void tcg_cpus_destroy(CPUState *cpu)
+void tcg_cpu_destroy(CPUState *cpu)
{
cpu_thread_signal_destroyed(cpu);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec()
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (22 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity Richard Henderson
` (10 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
tcg_cpus_exec() operates on a single vCPU, rename it
as 'tcg_cpu_exec'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240124101639.30056-4-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-accel-ops.h | 2 +-
accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
accel/tcg/tcg-accel-ops-rr.c | 2 +-
accel/tcg/tcg-accel-ops.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
index 17c7ed00eb..44c4079972 100644
--- a/accel/tcg/tcg-accel-ops.h
+++ b/accel/tcg/tcg-accel-ops.h
@@ -15,7 +15,7 @@
#include "sysemu/cpus.h"
void tcg_cpu_destroy(CPUState *cpu);
-int tcg_cpus_exec(CPUState *cpu);
+int tcg_cpu_exec(CPUState *cpu);
void tcg_handle_interrupt(CPUState *cpu, int mask);
void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
index bcba314a65..c552b45b8e 100644
--- a/accel/tcg/tcg-accel-ops-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -92,7 +92,7 @@ static void *mttcg_cpu_thread_fn(void *arg)
if (cpu_can_run(cpu)) {
int r;
bql_unlock();
- r = tcg_cpus_exec(cpu);
+ r = tcg_cpu_exec(cpu);
bql_lock();
switch (r) {
case EXCP_DEBUG:
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
index 0617f66b5b..894e73e52c 100644
--- a/accel/tcg/tcg-accel-ops-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -258,7 +258,7 @@ static void *rr_cpu_thread_fn(void *arg)
if (icount_enabled()) {
icount_prepare_for_run(cpu, cpu_budget);
}
- r = tcg_cpus_exec(cpu);
+ r = tcg_cpu_exec(cpu);
if (icount_enabled()) {
icount_process_data(cpu);
}
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 9b84b84218..9c957f421c 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -68,7 +68,7 @@ void tcg_cpu_destroy(CPUState *cpu)
cpu_thread_signal_destroyed(cpu);
}
-int tcg_cpus_exec(CPUState *cpu)
+int tcg_cpu_exec(CPUState *cpu)
{
int ret;
assert(tcg_enabled());
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (23 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Richard Henderson
` (9 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Convert packed logic to dumb icount_exit_request() helper.
No functional change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240124101639.30056-5-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 950dad63cb..f2535a2991 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -777,6 +777,17 @@ static inline bool need_replay_interrupt(int interrupt_request)
}
#endif /* !CONFIG_USER_ONLY */
+static inline bool icount_exit_request(CPUState *cpu)
+{
+ if (!icount_enabled()) {
+ return false;
+ }
+ if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) {
+ return false;
+ }
+ return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0;
+}
+
static inline bool cpu_handle_interrupt(CPUState *cpu,
TranslationBlock **last_tb)
{
@@ -882,10 +893,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
}
/* Finally, check if we need to exit to the main loop. */
- if (unlikely(qatomic_read(&cpu->exit_request))
- || (icount_enabled()
- && (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & CF_USE_ICOUNT)
- && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0)) {
+ if (unlikely(qatomic_read(&cpu->exit_request)) || icount_exit_request(cpu)) {
qatomic_set(&cpu->exit_request, 0);
if (cpu->exception_index == -1) {
cpu->exception_index = EXCP_INTERRUPT;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (24 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 16:24 ` Philippe Mathieu-Daudé
2024-01-28 4:42 ` [PATCH 27/33] target/loongarch: Constify loongarch_tcg_ops Richard Henderson
` (8 subsequent siblings)
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel
QEMU coding style recommends using structure typedefs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 5 +----
include/qemu/typedefs.h | 1 +
bsd-user/signal.c | 4 ++--
linux-user/signal.c | 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/tcg/cpu32.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 4 ++--
target/hexagon/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/loongarch/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
26 files changed, 29 insertions(+), 31 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index db58f12233..2c284d6397 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -90,9 +90,6 @@ typedef enum MMUAccessType {
typedef struct CPUWatchpoint CPUWatchpoint;
-/* see tcg-cpu-ops.h */
-struct TCGCPUOps;
-
/* see accel-cpu.h */
struct AccelCPUClass;
@@ -177,7 +174,7 @@ struct CPUClass {
const struct SysemuCPUOps *sysemu_ops;
/* when TCG is not available, this pointer is NULL */
- const struct TCGCPUOps *tcg_ops;
+ const TCGCPUOps *tcg_ops;
/*
* if not NULL, this is called in order for the CPUClass to initialize
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 5abdbc3874..d7c703b4ae 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -131,6 +131,7 @@ typedef struct Range Range;
typedef struct ReservedRegion ReservedRegion;
typedef struct SHPCDevice SHPCDevice;
typedef struct SSIBus SSIBus;
+typedef struct TCGCPUOps TCGCPUOps;
typedef struct TCGHelperInfo TCGHelperInfo;
typedef struct TranslationBlock TranslationBlock;
typedef struct VirtIODevice VirtIODevice;
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index ca31470772..f4352e4530 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -1022,7 +1022,7 @@ void process_pending_signals(CPUArchState *env)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
- const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@@ -1038,7 +1038,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
- const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);
diff --git a/linux-user/signal.c b/linux-user/signal.c
index c9527adfa3..d3e62ab030 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -671,7 +671,7 @@ void force_sigsegv(int oldsig)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
- const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@@ -687,7 +687,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
- const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index ce20a56270..80760be0f3 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -222,7 +222,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps alpha_tcg_ops = {
+static const TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
.restore_state_to_opc = alpha_restore_state_to_opc,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0ee9a879f0..e050928598 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2456,7 +2456,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
-static const struct TCGCPUOps arm_tcg_ops = {
+static const TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index d9e0e2a4dd..1125305115 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
-static const struct TCGCPUOps arm_v7m_tcg_ops = {
+static const TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 76dbe56284..41ff121d20 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -233,7 +233,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps avr_tcg_ops = {
+static const TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
.restore_state_to_opc = avr_restore_state_to_opc,
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 6512ef8ee2..93f26542d8 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -192,7 +192,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps crisv10_tcg_ops = {
+static const TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,
@@ -203,7 +203,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-static const struct TCGCPUOps crisv32_tcg_ops = {
+static const TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index b2bbb21b59..49f05eae99 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -358,7 +358,7 @@ static void hexagon_cpu_init(Object *obj)
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps hexagon_tcg_ops = {
+static const TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
.restore_state_to_opc = hexagon_restore_state_to_opc,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 2cc8e43b33..2d98082306 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -225,7 +225,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps hppa_tcg_ops = {
+static const TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
.restore_state_to_opc = hppa_restore_state_to_opc,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index e1405b7be9..8e148e9bc4 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps x86_tcg_ops = {
+static const TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.restore_state_to_opc = x86_restore_state_to_opc,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ea4281e177..d9ddab5b9a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps loongarch_tcg_ops = {
+static TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
.restore_state_to_opc = loongarch_restore_state_to_opc,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index f9dc447897..288140c986 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -546,7 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps m68k_tcg_ops = {
+static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
.restore_state_to_opc = m68k_restore_state_to_opc,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4c270e941f..171937564d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -410,7 +410,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps mb_tcg_ops = {
+static const TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.restore_state_to_opc = mb_restore_state_to_opc,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4c3e1ec2d9..dfe82f93ef 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -563,7 +563,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
* NB: cannot be const, as some elements are changed for specific
* mips hardware (see hw/mips/jazz.c).
*/
-static const struct TCGCPUOps mips_tcg_ops = {
+static const TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
.restore_state_to_opc = mips_restore_state_to_opc,
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 3e42889ce6..bff35f835a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -372,7 +372,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps nios2_tcg_ops = {
+static const TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
.restore_state_to_opc = nios2_restore_state_to_opc,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index fda0dc9470..bc54e7ccd0 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -235,7 +235,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps openrisc_tcg_ops = {
+static const TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
.restore_state_to_opc = openrisc_restore_state_to_opc,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 344196a8ce..23eb5522b6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps ppc_tcg_ops = {
+static const TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
.restore_state_to_opc = ppc_restore_state_to_opc,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 994ca1cdf9..b7da92783b 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
env->bins = data[1];
}
-static const struct TCGCPUOps riscv_tcg_ops = {
+static const TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.restore_state_to_opc = riscv_restore_state_to_opc,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index de1cc7a5e6..cfc97d06e7 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps rx_tcg_ops = {
+static const TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
.restore_state_to_opc = rx_restore_state_to_opc,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index db1590472e..b783e1e2e6 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -372,7 +372,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps s390_tcg_ops = {
+static const TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.restore_state_to_opc = s390x_restore_state_to_opc,
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index eb7eb6f30a..89a42e0e22 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -265,7 +265,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps superh_tcg_ops = {
+static const TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.restore_state_to_opc = superh_restore_state_to_opc,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 99d57cc209..8385c8a2b0 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -935,7 +935,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps sparc_tcg_ops = {
+static const TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
.restore_state_to_opc = sparc_restore_state_to_opc,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index dff88184c9..2f07fdbfab 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -190,7 +190,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps tricore_tcg_ops = {
+static const TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
.restore_state_to_opc = tricore_restore_state_to_opc,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index dfe0ff5c98..0da5409742 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -294,7 +294,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static const struct TCGCPUOps xtensa_tcg_ops = {
+static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 27/33] target/loongarch: Constify loongarch_tcg_ops
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (25 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c Richard Henderson
` (7 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d9ddab5b9a..d663d46b00 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static TCGCPUOps loongarch_tcg_ops = {
+static const TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
.restore_state_to_opc = loongarch_restore_state_to_opc,
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (26 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 27/33] target/loongarch: Constify loongarch_tcg_ops Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler Richard Henderson
` (6 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel
CPU_GET_CLASS does runtime type checking; use the cached
copy of the class instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 109 ++++++++++++++++++++++---------------------
1 file changed, 56 insertions(+), 53 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index f2535a2991..3aebf46849 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -343,9 +343,9 @@ static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc,
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- CPUClass *cc = CPU_GET_CLASS(cpu);
- assert(cc->tcg_ops->debug_check_breakpoint);
- match_bp = cc->tcg_ops->debug_check_breakpoint(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+ assert(tcg_ops->debug_check_breakpoint);
+ match_bp = tcg_ops->debug_check_breakpoint(cpu);
#endif
}
@@ -462,10 +462,11 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
* counter hit zero); we must restore the guest PC to the address
* of the start of the TB.
*/
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUClass *cc = cpu->cc;
+ const TCGCPUOps *tcg_ops = cc->tcg_ops;
- if (cc->tcg_ops->synchronize_from_tb) {
- cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
+ if (tcg_ops->synchronize_from_tb) {
+ tcg_ops->synchronize_from_tb(cpu, last_tb);
} else {
tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL));
assert(cc->set_pc);
@@ -497,19 +498,19 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
static void cpu_exec_enter(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
- if (cc->tcg_ops->cpu_exec_enter) {
- cc->tcg_ops->cpu_exec_enter(cpu);
+ if (tcg_ops->cpu_exec_enter) {
+ tcg_ops->cpu_exec_enter(cpu);
}
}
static void cpu_exec_exit(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
- if (cc->tcg_ops->cpu_exec_exit) {
- cc->tcg_ops->cpu_exec_exit(cpu);
+ if (tcg_ops->cpu_exec_exit) {
+ tcg_ops->cpu_exec_exit(cpu);
}
}
@@ -685,7 +686,7 @@ static inline bool cpu_handle_halt(CPUState *cpu)
static inline void cpu_handle_debug_exception(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
CPUWatchpoint *wp;
if (!cpu->watchpoint_hit) {
@@ -694,8 +695,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->tcg_ops->debug_excp_handler) {
- cc->tcg_ops->debug_excp_handler(cpu);
+ if (tcg_ops->debug_excp_handler) {
+ tcg_ops->debug_excp_handler(cpu);
}
}
@@ -712,6 +713,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
#endif
return false;
}
+
if (cpu->exception_index >= EXCP_INTERRUPT) {
/* exit request from the cpu execution loop */
*ret = cpu->exception_index;
@@ -720,43 +722,45 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
}
cpu->exception_index = -1;
return true;
- } else {
-#if defined(CONFIG_USER_ONLY)
- /* if user mode only, we simulate a fake exception
- which will be handled outside the cpu execution
- loop */
-#if defined(TARGET_I386)
- CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops->fake_user_interrupt(cpu);
-#endif /* TARGET_I386 */
- *ret = cpu->exception_index;
- cpu->exception_index = -1;
- return true;
-#else
- if (replay_exception()) {
- CPUClass *cc = CPU_GET_CLASS(cpu);
- bql_lock();
- cc->tcg_ops->do_interrupt(cpu);
- bql_unlock();
- cpu->exception_index = -1;
+ }
- if (unlikely(cpu->singlestep_enabled)) {
- /*
- * After processing the exception, ensure an EXCP_DEBUG is
- * raised when single-stepping so that GDB doesn't miss the
- * next instruction.
- */
- *ret = EXCP_DEBUG;
- cpu_handle_debug_exception(cpu);
- return true;
- }
- } else if (!replay_has_interrupt()) {
- /* give a chance to iothread in replay mode */
- *ret = EXCP_INTERRUPT;
+#if defined(CONFIG_USER_ONLY)
+ /*
+ * If user mode only, we simulate a fake exception which will be
+ * handled outside the cpu execution loop.
+ */
+#if defined(TARGET_I386)
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+ tcg_ops->fake_user_interrupt(cpu);
+#endif /* TARGET_I386 */
+ *ret = cpu->exception_index;
+ cpu->exception_index = -1;
+ return true;
+#else
+ if (replay_exception()) {
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+
+ bql_lock();
+ tcg_ops->do_interrupt(cpu);
+ bql_unlock();
+ cpu->exception_index = -1;
+
+ if (unlikely(cpu->singlestep_enabled)) {
+ /*
+ * After processing the exception, ensure an EXCP_DEBUG is
+ * raised when single-stepping so that GDB doesn't miss the
+ * next instruction.
+ */
+ *ret = EXCP_DEBUG;
+ cpu_handle_debug_exception(cpu);
return true;
}
-#endif
+ } else if (!replay_has_interrupt()) {
+ /* give a chance to iothread in replay mode */
+ *ret = EXCP_INTERRUPT;
+ return true;
}
+#endif
return false;
}
@@ -856,10 +860,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
- if (cc->tcg_ops->cpu_exec_interrupt &&
- cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (tcg_ops->cpu_exec_interrupt &&
+ tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
@@ -1078,10 +1082,9 @@ int cpu_exec(CPUState *cpu)
bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
{
static bool tcg_target_initialized;
- CPUClass *cc = CPU_GET_CLASS(cpu);
if (!tcg_target_initialized) {
- cc->tcg_ops->initialize();
+ cpu->cc->tcg_ops->initialize();
tcg_target_initialized = true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (27 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ Richard Henderson
` (5 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson, Pavel Dovgalyuk
From: Philippe Mathieu-Daudé <philmd@linaro.org>
In order to make accel/tcg/ target agnostic,
introduce the need_replay_interrupt() handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <20240124101639.30056-7-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 5 +++++
accel/tcg/cpu-exec.c | 8 +++++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 3ed279836f..013867b890 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -166,6 +166,11 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
+ /**
+ * @need_replay_interrupt: Return %true if @interrupt_request
+ * needs to be recorded for replay purposes.
+ */
+ bool (*need_replay_interrupt)(int interrupt_request);
#endif /* !CONFIG_USER_ONLY */
#endif /* NEED_CPU_H */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 3aebf46849..34d10eb173 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -771,12 +771,14 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
* "real" interrupt event later. It does not need to be recorded for
* replay purposes.
*/
-static inline bool need_replay_interrupt(int interrupt_request)
+static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request)
{
#if defined(TARGET_I386)
return !(interrupt_request & CPU_INTERRUPT_POLL);
#else
- return true;
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+ return !tcg_ops->need_replay_interrupt
+ || tcg_ops->need_replay_interrupt(interrupt_request);
#endif
}
#endif /* !CONFIG_USER_ONLY */
@@ -864,7 +866,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
if (tcg_ops->cpu_exec_interrupt &&
tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
- if (need_replay_interrupt(interrupt_request)) {
+ if (need_replay_interrupt(cpu, interrupt_request)) {
replay_interrupt();
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (28 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 31/33] accel/tcg: Inline need_replay_interrupt Richard Henderson
` (4 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson, Pavel Dovgalyuk
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move this x86-specific code out of the generic accel/tcg/.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240124101639.30056-8-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/helper-tcg.h | 1 +
accel/tcg/cpu-exec.c | 4 ----
target/i386/tcg/sysemu/seg_helper.c | 10 ++++++++++
target/i386/tcg/tcg-cpu.c | 1 +
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index ce34b737bb..253b1f561e 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
*/
void x86_cpu_do_interrupt(CPUState *cpu);
#ifndef CONFIG_USER_ONLY
+bool x86_need_replay_interrupt(int interrupt_request);
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
#endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 34d10eb173..2eacd694ea 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -773,13 +773,9 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
*/
static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request)
{
-#if defined(TARGET_I386)
- return !(interrupt_request & CPU_INTERRUPT_POLL);
-#else
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
return !tcg_ops->need_replay_interrupt
|| tcg_ops->need_replay_interrupt(interrupt_request);
-#endif
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c
index 1cb5a0db45..e6f42282bb 100644
--- a/target/i386/tcg/sysemu/seg_helper.c
+++ b/target/i386/tcg/sysemu/seg_helper.c
@@ -127,6 +127,16 @@ void x86_cpu_do_interrupt(CPUState *cs)
}
}
+bool x86_need_replay_interrupt(int interrupt_request)
+{
+ /*
+ * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
+ * "real" interrupt event later. It does not need to be recorded for
+ * replay purposes.
+ */
+ return !(interrupt_request & CPU_INTERRUPT_POLL);
+}
+
bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 8e148e9bc4..5bdcf45199 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -123,6 +123,7 @@ static const TCGCPUOps x86_tcg_ops = {
.do_unaligned_access = x86_cpu_do_unaligned_access,
.debug_excp_handler = breakpoint_handler,
.debug_check_breakpoint = x86_debug_check_breakpoint,
+ .need_replay_interrupt = x86_need_replay_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 31/33] accel/tcg: Inline need_replay_interrupt
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (29 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler Richard Henderson
` (3 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel
The function is now trivial, and with inlining we can
re-use the calling function's tcg_ops variable.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 2eacd694ea..75f7ba7bed 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -765,20 +765,6 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
return false;
}
-#ifndef CONFIG_USER_ONLY
-/*
- * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
- * "real" interrupt event later. It does not need to be recorded for
- * replay purposes.
- */
-static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request)
-{
- const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
- return !tcg_ops->need_replay_interrupt
- || tcg_ops->need_replay_interrupt(interrupt_request);
-}
-#endif /* !CONFIG_USER_ONLY */
-
static inline bool icount_exit_request(CPUState *cpu)
{
if (!icount_enabled()) {
@@ -862,7 +848,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
if (tcg_ops->cpu_exec_interrupt &&
tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
- if (need_replay_interrupt(cpu, interrupt_request)) {
+ if (!tcg_ops->need_replay_interrupt ||
+ tcg_ops->need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (30 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 31/33] accel/tcg: Inline need_replay_interrupt Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 4:42 ` [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ Richard Henderson
` (2 subsequent siblings)
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
In order to make accel/tcg/ target agnostic,
introduce the cpu_exec_halt() handler.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240124101639.30056-9-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 2 ++
accel/tcg/cpu-exec.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 013867b890..bf8ff8e3ee 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -112,6 +112,8 @@ struct TCGCPUOps {
void (*do_interrupt)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /** @cpu_exec_halt: Callback for handling halt in cpu_exec */
+ void (*cpu_exec_halt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss
*
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 75f7ba7bed..82627b12b8 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -664,6 +664,8 @@ static inline bool cpu_handle_halt(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
if (cpu->halted) {
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+
#if defined(TARGET_I386)
if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -673,6 +675,9 @@ static inline bool cpu_handle_halt(CPUState *cpu)
bql_unlock();
}
#endif /* TARGET_I386 */
+ if (tcg_ops->cpu_exec_halt) {
+ tcg_ops->cpu_exec_halt(cpu);
+ }
if (!cpu_has_work(cpu)) {
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (31 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler Richard Henderson
@ 2024-01-28 4:42 ` Richard Henderson
2024-01-28 6:30 ` [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
2024-01-28 16:30 ` Philippe Mathieu-Daudé
34 siblings, 0 replies; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 4:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Anton Johansson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move this x86-specific code out of the generic accel/tcg/.
Reported-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240124101639.30056-10-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/helper-tcg.h | 1 +
accel/tcg/cpu-exec.c | 12 ------------
target/i386/tcg/sysemu/seg_helper.c | 13 +++++++++++++
target/i386/tcg/tcg-cpu.c | 1 +
4 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index 253b1f561e..effc2c1c98 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
*/
void x86_cpu_do_interrupt(CPUState *cpu);
#ifndef CONFIG_USER_ONLY
+void x86_cpu_exec_halt(CPUState *cpu);
bool x86_need_replay_interrupt(int interrupt_request);
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
#endif
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 82627b12b8..977576ca14 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -30,9 +30,6 @@
#include "qemu/rcu.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
-#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
-#include "hw/i386/apic.h"
-#endif
#include "sysemu/cpus.h"
#include "exec/cpu-all.h"
#include "sysemu/cpu-timers.h"
@@ -666,15 +663,6 @@ static inline bool cpu_handle_halt(CPUState *cpu)
if (cpu->halted) {
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
-#if defined(TARGET_I386)
- if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
- X86CPU *x86_cpu = X86_CPU(cpu);
- bql_lock();
- apic_poll_irq(x86_cpu->apic_state);
- cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
- bql_unlock();
- }
-#endif /* TARGET_I386 */
if (tcg_ops->cpu_exec_halt) {
tcg_ops->cpu_exec_halt(cpu);
}
diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c
index e6f42282bb..2db8083748 100644
--- a/target/i386/tcg/sysemu/seg_helper.c
+++ b/target/i386/tcg/sysemu/seg_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
@@ -127,6 +128,18 @@ void x86_cpu_do_interrupt(CPUState *cs)
}
}
+void x86_cpu_exec_halt(CPUState *cpu)
+{
+ if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+
+ bql_lock();
+ apic_poll_irq(x86_cpu->apic_state);
+ cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
+ bql_unlock();
+ }
+}
+
bool x86_need_replay_interrupt(int interrupt_request)
{
/*
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 5bdcf45199..cca19cd40e 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -119,6 +119,7 @@ static const TCGCPUOps x86_tcg_ops = {
#else
.tlb_fill = x86_cpu_tlb_fill,
.do_interrupt = x86_cpu_do_interrupt,
+ .cpu_exec_halt = x86_cpu_exec_halt,
.cpu_exec_interrupt = x86_cpu_exec_interrupt,
.do_unaligned_access = x86_cpu_do_unaligned_access,
.debug_excp_handler = breakpoint_handler,
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH 00/33] tcg patch queue, pre-pull
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (32 preceding siblings ...)
2024-01-28 4:42 ` [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ Richard Henderson
@ 2024-01-28 6:30 ` Richard Henderson
2024-01-29 18:36 ` Philippe Mathieu-Daudé
2024-01-28 16:30 ` Philippe Mathieu-Daudé
34 siblings, 1 reply; 43+ messages in thread
From: Richard Henderson @ 2024-01-28 6:30 UTC (permalink / raw)
To: qemu-devel
On 1/28/24 14:41, Richard Henderson wrote:
> target: Uninline cpu_mmu_index()
> target: Uninline cpu_get_tb_cpu_state()
Dropping these two for now. The cpu_get_tb_cpu_state patch fails s390x --disable-tcg.
Both changes will be re-worked to introduce TCGCPUOps hooks immediately.
r~
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h
2024-01-28 4:42 ` [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Richard Henderson
@ 2024-01-28 16:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 28/1/24 05:42, Richard Henderson wrote:
> QEMU coding style recommends using structure typedefs.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/cpu.h | 5 +----
> include/qemu/typedefs.h | 1 +
> bsd-user/signal.c | 4 ++--
> linux-user/signal.c | 4 ++--
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/arm/tcg/cpu32.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/cris/cpu.c | 4 ++--
> target/hexagon/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/loongarch/cpu.c | 2 +-
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/nios2/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/ppc/cpu_init.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tricore/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 26 files changed, 29 insertions(+), 31 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD
2024-01-28 4:41 ` [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Richard Henderson
@ 2024-01-28 16:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 28/1/24 05:41, Richard Henderson wrote:
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Replace the manual rcu_read_(un)lock calls in cpu_exec().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Message-Id: <20240124074201.8239-2-philmd@linaro.org>
> [rth: Use RCU_READ_LOCK_GUARD not WITH_RCU_READ_LOCK_GUARD]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/cpu-exec.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 40c268bfa1..950dad63cb 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -1050,7 +1050,7 @@ int cpu_exec(CPUState *cpu)
> return EXCP_HALTED;
> }
>
> - rcu_read_lock();
> + RCU_READ_LOCK_GUARD();
> cpu_exec_enter(cpu);
>
> /*
> @@ -1064,8 +1064,6 @@ int cpu_exec(CPUState *cpu)
> ret = cpu_exec_setjmp(cpu, &sc);
>
> cpu_exec_exit(cpu);
> - rcu_read_unlock();
> -
> return ret;
> }
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() to common header
2024-01-28 4:41 ` [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() " Richard Henderson
@ 2024-01-28 16:29 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Anton Johansson
On 28/1/24 05:41, Richard Henderson wrote:
> From: Anton Johansson <anjo@rev.ng>
>
> Functions are target independent.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Message-Id: <20240119144024.14289-17-anjo@rev.ng>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-all.h | 25 -------------------------
> include/exec/cpu-common.h | 26 ++++++++++++++++++++++++++
> 2 files changed, 26 insertions(+), 25 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 00/33] tcg patch queue, pre-pull
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
` (33 preceding siblings ...)
2024-01-28 6:30 ` [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
@ 2024-01-28 16:30 ` Philippe Mathieu-Daudé
34 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:30 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 28/1/24 05:41, Richard Henderson wrote:
> Collect some patch sets, cherry-pick from others, with a few
> changes of my own. Patches that lack review:
>
> 26-include-qemu-Add-TCGCPUOps-typedef-to-typedefs.h.patch
> 27-target-loongarch-Constify-loongarch_tcg_ops.patch
> 28-accel-tcg-Use-CPUState.cc-instead-of-CPU_GET_CLASS-i.patch
> 31-accel-tcg-Inline-need_replay_interrupt.patch
>
>
> r~
>
>
> Anton Johansson (11):
> include/exec: Move vaddr defines to separate file
> hw/core: Include vaddr.h from cpu.h
> target: Use vaddr in gen_intermediate_code
> include/exec: Use vaddr in DisasContextBase for virtual addresses
> include/exec: typedef abi_ptr to vaddr
> target: Uninline cpu_mmu_index()
> target: Uninline cpu_get_tb_cpu_state()
> include/exec: Move PAGE_* macros to common header
> include/exec: Move cpu_*()/cpu_env() to common header
> include/hw/core: Move do_interrupt in TCGCPUOps
> include/hw/core: Remove i386 conditional on fake_user_interrupt
Nitpick: preferably s/^include\// in subject :)
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 07/33] target: Uninline cpu_mmu_index()
2024-01-28 4:41 ` [PATCH 07/33] target: Uninline cpu_mmu_index() Richard Henderson
@ 2024-01-28 16:41 ` Philippe Mathieu-Daudé
2024-01-28 16:45 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Anton Johansson
On 28/1/24 05:41, Richard Henderson wrote:
> From: Anton Johansson <anjo@rev.ng>
>
> Uninlines the target-defined cpu_mmu_index() function by moving its
> definition to target/*/cpu.c. This allows for compiling memory access
> functions in accel/tcg/cputlb.c without having to know target specifics.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Message-Id: <20240119144024.14289-13-anjo@rev.ng>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-common.h | 10 ++++++++++
> target/alpha/cpu.h | 9 ---------
> target/arm/cpu.h | 13 -------------
> target/avr/cpu.h | 7 -------
> target/cris/cpu.h | 4 ----
> target/hexagon/cpu.h | 9 ---------
> target/hppa/cpu.h | 13 -------------
> target/i386/cpu.h | 7 -------
> target/loongarch/cpu.h | 12 ------------
> target/m68k/cpu.h | 4 ----
> target/microblaze/cpu.h | 15 ---------------
> target/mips/cpu.h | 5 -----
> target/nios2/cpu.h | 6 ------
> target/openrisc/cpu.h | 12 ------------
> target/ppc/cpu.h | 8 --------
> target/riscv/cpu.h | 3 ---
> target/rx/cpu.h | 5 -----
> target/s390x/cpu.h | 31 -------------------------------
> target/sh4/cpu.h | 10 ----------
> target/sparc/cpu.h | 28 ----------------------------
> target/tricore/cpu.h | 5 -----
> target/xtensa/cpu.h | 5 -----
> target/alpha/cpu.c | 8 ++++++++
> target/arm/cpu.c | 5 +++++
> target/avr/cpu.c | 5 +++++
> target/cris/cpu.c | 4 ++++
> target/hexagon/cpu.c | 9 +++++++++
> target/hppa/cpu.c | 13 +++++++++++++
> target/i386/cpu.c | 7 +++++++
> target/loongarch/cpu.c | 12 ++++++++++++
> target/m68k/cpu.c | 5 +++++
> target/microblaze/cpu.c | 16 ++++++++++++++++
> target/mips/cpu.c | 5 +++++
> target/nios2/cpu.c | 6 ++++++
> target/openrisc/cpu.c | 12 ++++++++++++
> target/ppc/cpu.c | 9 +++++++++
> target/riscv/cpu_helper.c | 2 +-
> target/rx/cpu.c | 5 +++++
> target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++
> target/sh4/cpu.c | 13 +++++++++++++
> target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++
> target/tricore/cpu.c | 5 +++++
> target/xtensa/cpu.c | 4 ++++
> 43 files changed, 213 insertions(+), 212 deletions(-)
>
> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
> index 3109c6b67d..4724135f30 100644
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -34,6 +34,16 @@ void cpu_list_lock(void);
> void cpu_list_unlock(void);
> unsigned int cpu_list_generation_id_get(void);
>
> +/**
> + * cpu_mmu_index:
> + * @env: The cpu environment
> + * @ifetch: True for code access, false for data access.
> + *
> + * Return the core mmu index for the current translation regime.
> + * This function is used by generic TCG code paths.
> + */
> +int cpu_mmu_index(CPUArchState *env, bool ifetch);
> +
> void tcg_iommu_init_notifier_list(CPUState *cpu);
> void tcg_iommu_free_notifier_list(CPUState *cpu);
I'm kind of reluctant to use CPUArchState in a -common.h header
(except in include/hw/core/cpu.h::cpu_env).
Last Wednesday community call I mentioned to Anton I have a branch
going in the same direction he is taking, and suggested him to wait
to compare and unify our works.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 07/33] target: Uninline cpu_mmu_index()
2024-01-28 16:41 ` Philippe Mathieu-Daudé
@ 2024-01-28 16:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-28 16:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Anton Johansson
On 28/1/24 17:41, Philippe Mathieu-Daudé wrote:
> On 28/1/24 05:41, Richard Henderson wrote:
>> From: Anton Johansson <anjo@rev.ng>
>>
>> Uninlines the target-defined cpu_mmu_index() function by moving its
>> definition to target/*/cpu.c. This allows for compiling memory access
>> functions in accel/tcg/cputlb.c without having to know target specifics.
>>
>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>> Message-Id: <20240119144024.14289-13-anjo@rev.ng>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/exec/cpu-common.h | 10 ++++++++++
>> target/alpha/cpu.h | 9 ---------
>> target/arm/cpu.h | 13 -------------
>> target/avr/cpu.h | 7 -------
>> target/cris/cpu.h | 4 ----
>> target/hexagon/cpu.h | 9 ---------
>> target/hppa/cpu.h | 13 -------------
>> target/i386/cpu.h | 7 -------
>> target/loongarch/cpu.h | 12 ------------
>> target/m68k/cpu.h | 4 ----
>> target/microblaze/cpu.h | 15 ---------------
>> target/mips/cpu.h | 5 -----
>> target/nios2/cpu.h | 6 ------
>> target/openrisc/cpu.h | 12 ------------
>> target/ppc/cpu.h | 8 --------
>> target/riscv/cpu.h | 3 ---
>> target/rx/cpu.h | 5 -----
>> target/s390x/cpu.h | 31 -------------------------------
>> target/sh4/cpu.h | 10 ----------
>> target/sparc/cpu.h | 28 ----------------------------
>> target/tricore/cpu.h | 5 -----
>> target/xtensa/cpu.h | 5 -----
>> target/alpha/cpu.c | 8 ++++++++
>> target/arm/cpu.c | 5 +++++
>> target/avr/cpu.c | 5 +++++
>> target/cris/cpu.c | 4 ++++
>> target/hexagon/cpu.c | 9 +++++++++
>> target/hppa/cpu.c | 13 +++++++++++++
>> target/i386/cpu.c | 7 +++++++
>> target/loongarch/cpu.c | 12 ++++++++++++
>> target/m68k/cpu.c | 5 +++++
>> target/microblaze/cpu.c | 16 ++++++++++++++++
>> target/mips/cpu.c | 5 +++++
>> target/nios2/cpu.c | 6 ++++++
>> target/openrisc/cpu.c | 12 ++++++++++++
>> target/ppc/cpu.c | 9 +++++++++
>> target/riscv/cpu_helper.c | 2 +-
>> target/rx/cpu.c | 5 +++++
>> target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++
>> target/sh4/cpu.c | 13 +++++++++++++
>> target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++
>> target/tricore/cpu.c | 5 +++++
>> target/xtensa/cpu.c | 4 ++++
>> 43 files changed, 213 insertions(+), 212 deletions(-)
>>
>> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
>> index 3109c6b67d..4724135f30 100644
>> --- a/include/exec/cpu-common.h
>> +++ b/include/exec/cpu-common.h
>> @@ -34,6 +34,16 @@ void cpu_list_lock(void);
>> void cpu_list_unlock(void);
>> unsigned int cpu_list_generation_id_get(void);
>> +/**
>> + * cpu_mmu_index:
>> + * @env: The cpu environment
>> + * @ifetch: True for code access, false for data access.
>> + *
>> + * Return the core mmu index for the current translation regime.
>> + * This function is used by generic TCG code paths.
>> + */
>> +int cpu_mmu_index(CPUArchState *env, bool ifetch);
>> +
>> void tcg_iommu_init_notifier_list(CPUState *cpu);
>> void tcg_iommu_free_notifier_list(CPUState *cpu);
>
> I'm kind of reluctant to use CPUArchState in a -common.h header
> (except in include/hw/core/cpu.h::cpu_env).
>
> Last Wednesday community call I mentioned to Anton I have a branch
> going in the same direction he is taking, and suggested him to wait
> to compare and unify our works.
My bad I suppose, I should have replied to Anton series cover
to update you about the plan discussed during that call.
Also, if "This allows for compiling memory access functions in
accel/tcg/cputlb.c without having to know target specifics." I'd
rather see the corresponding meson change in the same patch.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 14/33] tests/tcg: Factor out gdbstub test functions
2024-01-28 4:41 ` [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Richard Henderson
@ 2024-01-29 9:38 ` Ilya Leoshkevich
0 siblings, 0 replies; 43+ messages in thread
From: Ilya Leoshkevich @ 2024-01-29 9:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, Alex Bennée
On Sun, Jan 28, 2024 at 02:41:54PM +1000, Richard Henderson wrote:
> From: Ilya Leoshkevich <iii@linux.ibm.com>
>
> Both the report() function as well as the initial gdbstub test sequence
> are copy-pasted into ~10 files with slight modifications. This
> indicates that they are indeed generic, so factor them out. While
> at it, add a few newlines to make the formatting closer to PEP-8.
>
> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
> Message-Id: <20240109230808.583012-3-iii@linux.ibm.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tests/guest-debug/run-test.py | 7 ++-
> tests/guest-debug/test_gdbstub.py | 56 +++++++++++++++++++
> tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 34 +----------
> tests/tcg/aarch64/gdbstub/test-sve.py | 33 +----------
> tests/tcg/multiarch/gdbstub/interrupt.py | 47 ++--------------
> tests/tcg/multiarch/gdbstub/memory.py | 39 +------------
> tests/tcg/multiarch/gdbstub/registers.py | 41 ++------------
> tests/tcg/multiarch/gdbstub/sha1.py | 38 ++-----------
> .../multiarch/gdbstub/test-proc-mappings.py | 39 +------------
> .../multiarch/gdbstub/test-qxfer-auxv-read.py | 37 +-----------
> .../gdbstub/test-thread-breakpoint.py | 37 +-----------
> tests/tcg/s390x/gdbstub/test-signals-s390x.py | 42 +-------------
> tests/tcg/s390x/gdbstub/test-svc.py | 39 +------------
> 13 files changed, 94 insertions(+), 395 deletions(-)
> create mode 100644 tests/guest-debug/test_gdbstub.py
Alex had issues with this and the next patch, I posted an update that
hopefully resolves them:
https://lore.kernel.org/qemu-devel/20240129093410.3151-1-iii@linux.ibm.com/
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH 00/33] tcg patch queue, pre-pull
2024-01-28 6:30 ` [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
@ 2024-01-29 18:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-29 18:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: Anton Johansson, qemu-devel
On 28/1/24 07:30, Richard Henderson wrote:
> On 1/28/24 14:41, Richard Henderson wrote:
>> target: Uninline cpu_mmu_index()
>> target: Uninline cpu_get_tb_cpu_state()
>
> Dropping these two for now.
Good news! (for me at least)
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2024-01-29 18:38 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-28 4:41 [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
2024-01-28 4:41 ` [PATCH 01/33] cpu-exec: simplify jump cache management Richard Henderson
2024-01-28 4:41 ` [PATCH 02/33] include/exec: Move vaddr defines to separate file Richard Henderson
2024-01-28 4:41 ` [PATCH 03/33] hw/core: Include vaddr.h from cpu.h Richard Henderson
2024-01-28 4:41 ` [PATCH 04/33] target: Use vaddr in gen_intermediate_code Richard Henderson
2024-01-28 4:41 ` [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses Richard Henderson
2024-01-28 4:41 ` [PATCH 06/33] include/exec: typedef abi_ptr to vaddr Richard Henderson
2024-01-28 4:41 ` [PATCH 07/33] target: Uninline cpu_mmu_index() Richard Henderson
2024-01-28 16:41 ` Philippe Mathieu-Daudé
2024-01-28 16:45 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state() Richard Henderson
2024-01-28 4:41 ` [PATCH 09/33] include/exec: Move PAGE_* macros to common header Richard Henderson
2024-01-28 4:41 ` [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() " Richard Henderson
2024-01-28 16:29 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps Richard Henderson
2024-01-28 4:41 ` [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt Richard Henderson
2024-01-28 4:41 ` [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection Richard Henderson
2024-01-28 4:41 ` [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Richard Henderson
2024-01-29 9:38 ` Ilya Leoshkevich
2024-01-28 4:41 ` [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test Richard Henderson
2024-01-28 4:41 ` [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Richard Henderson
2024-01-28 16:27 ` Philippe Mathieu-Daudé
2024-01-28 4:41 ` [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user Richard Henderson
2024-01-28 4:41 ` [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c Richard Henderson
2024-01-28 4:41 ` [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code Richard Henderson
2024-01-28 4:42 ` [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c Richard Henderson
2024-01-28 4:42 ` [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/ Richard Henderson
2024-01-28 4:42 ` [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson Richard Henderson
2024-01-28 4:42 ` [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() Richard Henderson
2024-01-28 4:42 ` [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() Richard Henderson
2024-01-28 4:42 ` [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity Richard Henderson
2024-01-28 4:42 ` [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Richard Henderson
2024-01-28 16:24 ` Philippe Mathieu-Daudé
2024-01-28 4:42 ` [PATCH 27/33] target/loongarch: Constify loongarch_tcg_ops Richard Henderson
2024-01-28 4:42 ` [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c Richard Henderson
2024-01-28 4:42 ` [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler Richard Henderson
2024-01-28 4:42 ` [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ Richard Henderson
2024-01-28 4:42 ` [PATCH 31/33] accel/tcg: Inline need_replay_interrupt Richard Henderson
2024-01-28 4:42 ` [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler Richard Henderson
2024-01-28 4:42 ` [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ Richard Henderson
2024-01-28 6:30 ` [PATCH 00/33] tcg patch queue, pre-pull Richard Henderson
2024-01-29 18:36 ` Philippe Mathieu-Daudé
2024-01-28 16:30 ` Philippe Mathieu-Daudé
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