From: Andrew Jones <ajones@ventanamicro.com>
To: Vadim Shakirov <vadim.shakirov@syntacore.com>
Cc: qemu-devel@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit
Date: Mon, 29 Jan 2024 10:30:24 +0100 [thread overview]
Message-ID: <20240129-01580d76b59950a405002ea7@orel> (raw)
In-Reply-To: <20240129084728.48311-1-vadim.shakirov@syntacore.com>
On Mon, Jan 29, 2024 at 11:47:28AM +0300, Vadim Shakirov wrote:
> mcountinhibit, mcounteren and scounteren must always be 32-bit by
> privileged spec
We should also change hcounteren.
Thanks,
drew
>
> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
> ---
> target/riscv/cpu.h | 6 +++---
> target/riscv/machine.c | 10 +++++-----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5138187727..2236a55bf1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -334,10 +334,10 @@ struct CPUArchState {
> */
> bool two_stage_indirect_lookup;
>
> - target_ulong scounteren;
> - target_ulong mcounteren;
> + uint32_t scounteren;
> + uint32_t mcounteren;
>
> - target_ulong mcountinhibit;
> + uint32_t mcountinhibit;
>
> /* PMU counter state */
> PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 72fe2374dc..6bf013054d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -354,8 +354,8 @@ static const VMStateDescription vmstate_jvt = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 9,
> - .minimum_version_id = 9,
> + .version_id = 10,
> + .minimum_version_id = 10,
> .post_load = riscv_cpu_post_load,
> .fields = (const VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> VMSTATE_UINTTL(env.miselect, RISCVCPU),
> VMSTATE_UINTTL(env.siselect, RISCVCPU),
> - VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> + VMSTATE_UINT32(env.scounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
> VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
> vmstate_pmu_ctr_state, PMUCTRState),
> VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
> --
> 2.34.1
>
>
prev parent reply other threads:[~2024-01-29 9:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-29 8:47 [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit Vadim Shakirov
2024-01-29 9:30 ` Andrew Jones [this message]
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