* [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit
@ 2024-01-29 8:47 Vadim Shakirov
2024-01-29 9:30 ` Andrew Jones
0 siblings, 1 reply; 2+ messages in thread
From: Vadim Shakirov @ 2024-01-29 8:47 UTC (permalink / raw)
To: qemu-devel
Cc: Vadim Shakirov, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv
mcountinhibit, mcounteren and scounteren must always be 32-bit by
privileged spec
Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/machine.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5138187727..2236a55bf1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -334,10 +334,10 @@ struct CPUArchState {
*/
bool two_stage_indirect_lookup;
- target_ulong scounteren;
- target_ulong mcounteren;
+ uint32_t scounteren;
+ uint32_t mcounteren;
- target_ulong mcountinhibit;
+ uint32_t mcountinhibit;
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 72fe2374dc..6bf013054d 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -354,8 +354,8 @@ static const VMStateDescription vmstate_jvt = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 9,
- .minimum_version_id = 9,
+ .version_id = 10,
+ .minimum_version_id = 10,
.post_load = riscv_cpu_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.miselect, RISCVCPU),
VMSTATE_UINTTL(env.siselect, RISCVCPU),
- VMSTATE_UINTTL(env.scounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
+ VMSTATE_UINT32(env.scounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState),
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit
2024-01-29 8:47 [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit Vadim Shakirov
@ 2024-01-29 9:30 ` Andrew Jones
0 siblings, 0 replies; 2+ messages in thread
From: Andrew Jones @ 2024-01-29 9:30 UTC (permalink / raw)
To: Vadim Shakirov
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv
On Mon, Jan 29, 2024 at 11:47:28AM +0300, Vadim Shakirov wrote:
> mcountinhibit, mcounteren and scounteren must always be 32-bit by
> privileged spec
We should also change hcounteren.
Thanks,
drew
>
> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
> ---
> target/riscv/cpu.h | 6 +++---
> target/riscv/machine.c | 10 +++++-----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5138187727..2236a55bf1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -334,10 +334,10 @@ struct CPUArchState {
> */
> bool two_stage_indirect_lookup;
>
> - target_ulong scounteren;
> - target_ulong mcounteren;
> + uint32_t scounteren;
> + uint32_t mcounteren;
>
> - target_ulong mcountinhibit;
> + uint32_t mcountinhibit;
>
> /* PMU counter state */
> PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 72fe2374dc..6bf013054d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -354,8 +354,8 @@ static const VMStateDescription vmstate_jvt = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 9,
> - .minimum_version_id = 9,
> + .version_id = 10,
> + .minimum_version_id = 10,
> .post_load = riscv_cpu_post_load,
> .fields = (const VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> VMSTATE_UINTTL(env.miselect, RISCVCPU),
> VMSTATE_UINTTL(env.siselect, RISCVCPU),
> - VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> + VMSTATE_UINT32(env.scounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcounteren, RISCVCPU),
> + VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
> VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
> vmstate_pmu_ctr_state, PMUCTRState),
> VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2024-01-29 9:31 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-29 8:47 [PATCH v2] target/riscv: mcountinhibit, mcounteren and scounteren always 32-bit Vadim Shakirov
2024-01-29 9:30 ` Andrew Jones
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).