From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org
Cc: mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com,
shannon.zhaosl@gmail.com, jeeheng.sia@starfivetech.com,
peter.maydell@linaro.org, sunilvl@ventanamicro.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, liwei1518@gmail.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com
Subject: [RESEND RFC 3/3] hw/arm/virt-acpi-build.c: Enable CPU cache topology
Date: Mon, 29 Jan 2024 02:40:39 -0800 [thread overview]
Message-ID: <20240129104039.117671-4-jeeheng.sia@starfivetech.com> (raw)
In-Reply-To: <20240129104039.117671-1-jeeheng.sia@starfivetech.com>
Introduced a 3-layer cache for the ARM virtual machine.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
---
hw/arm/virt-acpi-build.c | 44 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 17aeec7a6f..c57067cd63 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -426,6 +426,48 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
g_array_free(its_idmaps, true);
}
+static void pptt_setup(GArray *table_data, BIOSLinker *linker, MachineState *ms,
+ const char *oem_id, const char *oem_table_id)
+{
+ CPUCaches default_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ .type = DATA_CACHE,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .sets = 256,
+ .attributes = 0x02,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ .type = INSTRUCTION_CACHE,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .sets = 256,
+ .attributes = 0x04,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .size = 2048 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .sets = 4096,
+ .attributes = 0x0a,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .size = 4096 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .sets = 8192,
+ .attributes = 0x0a,
+ },
+ };
+
+ build_pptt(table_data, linker, ms, oem_id, oem_table_id,
+ &default_cache_info);
+}
+
/*
* Serial Port Console Redirection Table (SPCR)
* Rev: 1.07
@@ -912,7 +954,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
if (!vmc->no_cpu_topology) {
acpi_add_table(table_offsets, tables_blob);
- build_pptt(tables_blob, tables->linker, ms,
+ pptt_setup(tables_blob, tables->linker, ms,
vms->oem_id, vms->oem_table_id);
}
--
2.34.1
prev parent reply other threads:[~2024-01-29 10:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-29 10:40 [RESEND RFC 0/3] Add cache structure table creation for PPTT table Sia Jee Heng
2024-01-29 10:40 ` [RESEND RFC 1/3] hw/acpi/aml-build: " Sia Jee Heng
2024-01-29 10:40 ` [RESEND RFC 2/3] hw/riscv/virt-acpi-build.c: Generate " Sia Jee Heng
2024-01-29 10:40 ` Sia Jee Heng [this message]
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