* [PATCH v4 1/2] hw/ssi: Implement BCM2835 SPI Controller
2024-01-29 22:18 [PATCH v4 0/2] Add BCM2835-SPI0 to BCM2835 Rayhan Faizel
@ 2024-01-29 22:18 ` Rayhan Faizel
2024-01-29 22:18 ` [PATCH v4 2/2] hw/arm: Connect SPI Controller to BCM2835 Rayhan Faizel
2024-02-02 13:51 ` [PATCH v4 0/2] Add BCM2835-SPI0 " Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Rayhan Faizel @ 2024-01-29 22:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, philmd, alistair, pbonzini, qemu-arm,
Rayhan Faizel
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
---
docs/system/arm/raspi.rst | 2 +-
hw/ssi/Kconfig | 4 +
hw/ssi/bcm2835_spi.c | 288 +++++++++++++++++++++++++++++++++++
hw/ssi/meson.build | 1 +
include/hw/ssi/bcm2835_spi.h | 81 ++++++++++
5 files changed, 375 insertions(+), 1 deletion(-)
create mode 100644 hw/ssi/bcm2835_spi.c
create mode 100644 include/hw/ssi/bcm2835_spi.h
diff --git a/docs/system/arm/raspi.rst b/docs/system/arm/raspi.rst
index 922fe375a6..d0a6f08b2b 100644
--- a/docs/system/arm/raspi.rst
+++ b/docs/system/arm/raspi.rst
@@ -33,11 +33,11 @@ Implemented devices
* USB2 host controller (DWC2 and MPHI)
* MailBox controller (MBOX)
* VideoCore firmware (property)
+ * Peripheral SPI controller (SPI)
Missing devices
---------------
- * Peripheral SPI controller (SPI)
* Analog to Digital Converter (ADC)
* Pulse Width Modulation (PWM)
diff --git a/hw/ssi/Kconfig b/hw/ssi/Kconfig
index 7d90a02181..83ee53c1d0 100644
--- a/hw/ssi/Kconfig
+++ b/hw/ssi/Kconfig
@@ -20,3 +20,7 @@ config XILINX_SPIPS
config STM32F2XX_SPI
bool
select SSI
+
+config BCM2835_SPI
+ bool
+ select SSI
diff --git a/hw/ssi/bcm2835_spi.c b/hw/ssi/bcm2835_spi.c
new file mode 100644
index 0000000000..6ecb42d4e3
--- /dev/null
+++ b/hw/ssi/bcm2835_spi.c
@@ -0,0 +1,288 @@
+/*
+ * BCM2835 SPI Master Controller
+ *
+ * Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/fifo8.h"
+#include "hw/ssi/bcm2835_spi.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+
+static void bcm2835_spi_update_int(BCM2835SPIState *s)
+{
+ int do_interrupt = 0;
+
+ /* Interrupt on DONE */
+ if (s->cs & BCM2835_SPI_CS_INTD && s->cs & BCM2835_SPI_CS_DONE) {
+ do_interrupt = 1;
+ }
+ /* Interrupt on RXR */
+ if (s->cs & BCM2835_SPI_CS_INTR && s->cs & BCM2835_SPI_CS_RXR) {
+ do_interrupt = 1;
+ }
+ qemu_set_irq(s->irq, do_interrupt);
+}
+
+static void bcm2835_spi_update_rx_flags(BCM2835SPIState *s)
+{
+ /* Set RXD if RX FIFO is non empty */
+ if (!fifo8_is_empty(&s->rx_fifo)) {
+ s->cs |= BCM2835_SPI_CS_RXD;
+ } else {
+ s->cs &= ~BCM2835_SPI_CS_RXD;
+ }
+
+ /* Set RXF if RX FIFO is full */
+ if (fifo8_is_full(&s->rx_fifo)) {
+ s->cs |= BCM2835_SPI_CS_RXF;
+ } else {
+ s->cs &= ~BCM2835_SPI_CS_RXF;
+ }
+
+ /* Set RXR if RX FIFO is 3/4th used or above */
+ if (fifo8_num_used(&s->rx_fifo) >= FIFO_SIZE_3_4) {
+ s->cs |= BCM2835_SPI_CS_RXR;
+ } else {
+ s->cs &= ~BCM2835_SPI_CS_RXR;
+ }
+}
+
+static void bcm2835_spi_update_tx_flags(BCM2835SPIState *s)
+{
+ /* Set TXD if TX FIFO is not full */
+ if (fifo8_is_full(&s->tx_fifo)) {
+ s->cs &= ~BCM2835_SPI_CS_TXD;
+ } else {
+ s->cs |= BCM2835_SPI_CS_TXD;
+ }
+
+ /* Set DONE if in TA mode and TX FIFO is empty */
+ if (fifo8_is_empty(&s->tx_fifo) && s->cs & BCM2835_SPI_CS_TA) {
+ s->cs |= BCM2835_SPI_CS_DONE;
+ } else {
+ s->cs &= ~BCM2835_SPI_CS_DONE;
+ }
+}
+
+static void bcm2835_spi_flush_tx_fifo(BCM2835SPIState *s)
+{
+ uint8_t tx_byte, rx_byte;
+
+ while (!fifo8_is_empty(&s->tx_fifo) && !fifo8_is_full(&s->rx_fifo)) {
+ tx_byte = fifo8_pop(&s->tx_fifo);
+ rx_byte = ssi_transfer(s->bus, tx_byte);
+ fifo8_push(&s->rx_fifo, rx_byte);
+ }
+
+ bcm2835_spi_update_tx_flags(s);
+ bcm2835_spi_update_rx_flags(s);
+}
+
+static uint64_t bcm2835_spi_read(void *opaque, hwaddr addr, unsigned size)
+{
+ BCM2835SPIState *s = opaque;
+ uint32_t readval = 0;
+
+ switch (addr) {
+ case BCM2835_SPI_CS:
+ readval = s->cs & 0xffffffff;
+ break;
+ case BCM2835_SPI_FIFO:
+ bcm2835_spi_flush_tx_fifo(s);
+ if (s->cs & BCM2835_SPI_CS_RXD) {
+ readval = fifo8_pop(&s->rx_fifo);
+ bcm2835_spi_update_rx_flags(s);
+ }
+
+ bcm2835_spi_update_int(s);
+ break;
+ case BCM2835_SPI_CLK:
+ readval = s->clk & 0xffff;
+ break;
+ case BCM2835_SPI_DLEN:
+ readval = s->dlen & 0xffff;
+ break;
+ case BCM2835_SPI_LTOH:
+ readval = s->ltoh & 0xf;
+ break;
+ case BCM2835_SPI_DC:
+ readval = s->dc & 0xffffffff;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+ return readval;
+}
+
+static void bcm2835_spi_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
+{
+ BCM2835SPIState *s = opaque;
+
+ switch (addr) {
+ case BCM2835_SPI_CS:
+ s->cs = (value & ~RO_MASK) | (s->cs & RO_MASK);
+ if (!(s->cs & BCM2835_SPI_CS_TA)) {
+ /* Clear DONE and RXR if TA is off */
+ s->cs &= ~(BCM2835_SPI_CS_DONE);
+ s->cs &= ~(BCM2835_SPI_CS_RXR);
+ }
+
+ /* Clear RX FIFO */
+ if (s->cs & BCM2835_SPI_CLEAR_RX) {
+ fifo8_reset(&s->rx_fifo);
+ bcm2835_spi_update_rx_flags(s);
+ }
+
+ /* Clear TX FIFO*/
+ if (s->cs & BCM2835_SPI_CLEAR_TX) {
+ fifo8_reset(&s->tx_fifo);
+ bcm2835_spi_update_tx_flags(s);
+ }
+
+ /* Set Transfer Active */
+ if (s->cs & BCM2835_SPI_CS_TA) {
+ bcm2835_spi_update_tx_flags(s);
+ }
+
+ if (s->cs & BCM2835_SPI_CS_DMAEN) {
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "DMA not supported\n", __func__);
+ }
+
+ if (s->cs & BCM2835_SPI_CS_LEN) {
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "LoSSI not supported\n", __func__);
+ }
+
+ bcm2835_spi_update_int(s);
+ break;
+ case BCM2835_SPI_FIFO:
+ /*
+ * According to documentation, writes to FIFO without TA controls
+ * CS and DLEN registers. This is supposed to be used in DMA mode
+ * which is currently unimplemented. Moreover, Linux does not make
+ * use of this and directly modifies the CS and DLEN registers.
+ */
+ if (s->cs & BCM2835_SPI_CS_TA) {
+ if (s->cs & BCM2835_SPI_CS_TXD) {
+ fifo8_push(&s->tx_fifo, value & 0xff);
+ bcm2835_spi_update_tx_flags(s);
+ }
+
+ bcm2835_spi_flush_tx_fifo(s);
+ bcm2835_spi_update_int(s);
+ }
+ break;
+ case BCM2835_SPI_CLK:
+ s->clk = value & 0xffff;
+ break;
+ case BCM2835_SPI_DLEN:
+ s->dlen = value & 0xffff;
+ break;
+ case BCM2835_SPI_LTOH:
+ s->ltoh = value & 0xf;
+ break;
+ case BCM2835_SPI_DC:
+ s->dc = value & 0xffffffff;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps bcm2835_spi_ops = {
+ .read = bcm2835_spi_read,
+ .write = bcm2835_spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void bcm2835_spi_realize(DeviceState *dev, Error **errp)
+{
+ BCM2835SPIState *s = BCM2835_SPI(dev);
+ s->bus = ssi_create_bus(dev, "spi");
+
+ memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_spi_ops, s,
+ TYPE_BCM2835_SPI, 0x18);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ fifo8_create(&s->tx_fifo, FIFO_SIZE);
+ fifo8_create(&s->rx_fifo, FIFO_SIZE);
+}
+static void bcm2835_spi_reset(DeviceState *dev)
+{
+ BCM2835SPIState *s = BCM2835_SPI(dev);
+
+ fifo8_reset(&s->tx_fifo);
+ fifo8_reset(&s->rx_fifo);
+
+ /* Reset values according to BCM2835 Peripheral Documentation */
+ s->cs = BCM2835_SPI_CS_TXD | BCM2835_SPI_CS_REN;
+ s->clk = 0;
+ s->dlen = 0;
+ s->ltoh = 0x1;
+ s->dc = 0x30201020;
+}
+
+static const VMStateDescription vmstate_bcm2835_spi = {
+ .name = TYPE_BCM2835_SPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_FIFO8(tx_fifo, BCM2835SPIState),
+ VMSTATE_FIFO8(rx_fifo, BCM2835SPIState),
+ VMSTATE_UINT32(cs, BCM2835SPIState),
+ VMSTATE_UINT32(clk, BCM2835SPIState),
+ VMSTATE_UINT32(dlen, BCM2835SPIState),
+ VMSTATE_UINT32(ltoh, BCM2835SPIState),
+ VMSTATE_UINT32(dc, BCM2835SPIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void bcm2835_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = bcm2835_spi_reset;
+ dc->realize = bcm2835_spi_realize;
+ dc->vmsd = &vmstate_bcm2835_spi;
+}
+
+static const TypeInfo bcm2835_spi_info = {
+ .name = TYPE_BCM2835_SPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835SPIState),
+ .class_init = bcm2835_spi_class_init,
+};
+
+static void bcm2835_spi_register_types(void)
+{
+ type_register_static(&bcm2835_spi_info);
+}
+
+type_init(bcm2835_spi_register_types)
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index 0aebcdd614..b999aeb027 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -11,3 +11,4 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-ospi.c'))
system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c'))
system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c'))
system_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_spi_host.c'))
+system_ss.add(when: 'CONFIG_BCM2835_SPI', if_true: files('bcm2835_spi.c'))
diff --git a/include/hw/ssi/bcm2835_spi.h b/include/hw/ssi/bcm2835_spi.h
new file mode 100644
index 0000000000..d3f8cec111
--- /dev/null
+++ b/include/hw/ssi/bcm2835_spi.h
@@ -0,0 +1,81 @@
+/*
+ * BCM2835 SPI Master Controller
+ *
+ * Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ssi/ssi.h"
+#include "qom/object.h"
+#include "qemu/fifo8.h"
+
+#define TYPE_BCM2835_SPI "bcm2835-spi"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SPIState, BCM2835_SPI)
+
+/*
+ * Though BCM2835 documentation says FIFOs have a capacity of 16,
+ * FIFOs are actually 16 words in size or effectively 64 bytes when operating
+ * in non DMA mode.
+ */
+#define FIFO_SIZE 64
+#define FIFO_SIZE_3_4 48
+
+#define RO_MASK 0x1f0000
+
+#define BCM2835_SPI_CS 0x00
+#define BCM2835_SPI_FIFO 0x04
+#define BCM2835_SPI_CLK 0x08
+#define BCM2835_SPI_DLEN 0x0c
+#define BCM2835_SPI_LTOH 0x10
+#define BCM2835_SPI_DC 0x14
+
+#define BCM2835_SPI_CS_RXF BIT(20)
+#define BCM2835_SPI_CS_RXR BIT(19)
+#define BCM2835_SPI_CS_TXD BIT(18)
+#define BCM2835_SPI_CS_RXD BIT(17)
+#define BCM2835_SPI_CS_DONE BIT(16)
+#define BCM2835_SPI_CS_LEN BIT(13)
+#define BCM2835_SPI_CS_REN BIT(12)
+#define BCM2835_SPI_CS_INTR BIT(10)
+#define BCM2835_SPI_CS_INTD BIT(9)
+#define BCM2835_SPI_CS_DMAEN BIT(8)
+#define BCM2835_SPI_CS_TA BIT(7)
+#define BCM2835_SPI_CLEAR_RX BIT(5)
+#define BCM2835_SPI_CLEAR_TX BIT(4)
+
+struct BCM2835SPIState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ SSIBus *bus;
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ uint32_t cs;
+ uint32_t clk;
+ uint32_t dlen;
+ uint32_t ltoh;
+ uint32_t dc;
+
+ Fifo8 tx_fifo;
+ Fifo8 rx_fifo;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v4 2/2] hw/arm: Connect SPI Controller to BCM2835
2024-01-29 22:18 [PATCH v4 0/2] Add BCM2835-SPI0 to BCM2835 Rayhan Faizel
2024-01-29 22:18 ` [PATCH v4 1/2] hw/ssi: Implement BCM2835 SPI Controller Rayhan Faizel
@ 2024-01-29 22:18 ` Rayhan Faizel
2024-02-02 13:51 ` [PATCH v4 0/2] Add BCM2835-SPI0 " Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Rayhan Faizel @ 2024-01-29 22:18 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, philmd, alistair, pbonzini, qemu-arm,
Rayhan Faizel
This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.
Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
---
hw/arm/Kconfig | 1 +
hw/arm/bcm2835_peripherals.c | 16 +++++++++++++++-
include/hw/arm/bcm2835_peripherals.h | 3 ++-
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 218b454e97..c8e0f2d78c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -425,6 +425,7 @@ config RASPI
select PL011 # UART
select SDHCI
select USB_DWC2
+ select BCM2835_SPI
config STM32F100_SOC
bool
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 0233038b95..6b94bffb9b 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -144,6 +144,10 @@ static void bcm2835_peripherals_init(Object *obj)
/* Power Management */
object_initialize_child(obj, "powermgt", &s->powermgt,
TYPE_BCM2835_POWERMGT);
+
+ /* SPI */
+ object_initialize_child(obj, "bcm2835-spi0", &s->spi[0],
+ TYPE_BCM2835_SPI);
}
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -402,11 +406,21 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+ /* SPI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[0]), errp)) {
+ return;
+ }
+
+ memory_region_add_subregion(&s->peri_mr, SPI0_OFFSET,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi[0]), 0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[0]), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
+ INTERRUPT_SPI));
+
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
- create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100);
create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20);
create_unimp(s, &s->i2c[1], "bcm2835-i2c1", BSC1_OFFSET, 0x20);
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index d724a2fc28..0203bb79d8 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -31,6 +31,7 @@
#include "hw/gpio/bcm2835_gpio.h"
#include "hw/timer/bcm2835_systmr.h"
#include "hw/usb/hcd-dwc2.h"
+#include "hw/ssi/bcm2835_spi.h"
#include "hw/misc/unimp.h"
#include "qom/object.h"
@@ -66,7 +67,7 @@ struct BCM2835PeripheralState {
BCM2835GpioState gpio;
Bcm2835ThermalState thermal;
UnimplementedDeviceState i2s;
- UnimplementedDeviceState spi[1];
+ BCM2835SPIState spi[1];
UnimplementedDeviceState i2c[3];
UnimplementedDeviceState otp;
UnimplementedDeviceState dbus;
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread