From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/36] target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
Date: Fri, 2 Feb 2024 15:36:10 +0000 [thread overview]
Message-ID: <20240202153637.3710444-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20240202153637.3710444-1-peter.maydell@linaro.org>
In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to
userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID
register fields which it exposes to userspace. Update our
exported_bits mask to include this.
(This doesn't yet change any behaviour for us, because we don't yet
have any CPUs that implement this feature, which is part of SVE2.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240125134304.1470404-1-peter.maydell@linaro.org
---
target/arm/helper.c | 1 +
tests/tcg/aarch64/sysregs.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a0041aa0ec7..d51093a7c44 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8897,6 +8897,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
R_ID_AA64ZFR0_AES_MASK |
R_ID_AA64ZFR0_BITPERM_MASK |
R_ID_AA64ZFR0_BFLOAT16_MASK |
+ R_ID_AA64ZFR0_B16B16_MASK |
R_ID_AA64ZFR0_SHA3_MASK |
R_ID_AA64ZFR0_SM4_MASK |
R_ID_AA64ZFR0_I8MM_MASK |
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
index f7a055f1d5f..301e61d0dd4 100644
--- a/tests/tcg/aarch64/sysregs.c
+++ b/tests/tcg/aarch64/sysregs.c
@@ -137,7 +137,7 @@ int main(void)
/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
get_cpu_reg_check_zero(id_aa64dfr1_el1);
- get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff));
+ get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,0fff,00ff));
get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(8ff1,fcff,0000,0000));
get_cpu_reg_check_zero(id_aa64afr0_el1);
--
2.34.1
next prev parent reply other threads:[~2024-02-02 15:39 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 15:36 [PULL 00/36] target-arm queue Peter Maydell
2024-02-02 15:36 ` [PULL 01/36] target/arm: fix exception syndrome for AArch32 bkpt insn Peter Maydell
2024-02-02 15:36 ` [PULL 02/36] pci: Switch bus reset to 3-phase-reset Peter Maydell
2024-02-02 15:36 ` [PULL 03/36] vmbus: " Peter Maydell
2024-02-02 15:36 ` [PULL 04/36] adb: " Peter Maydell
2024-02-02 15:36 ` [PULL 05/36] hw/s390x/css-bridge: switch virtual-css bus " Peter Maydell
2024-02-02 15:36 ` [PULL 06/36] hw/core: Remove transitional infrastructure from BusClass Peter Maydell
2024-02-02 15:36 ` [PULL 07/36] system/vl.c: Fix handling of '-serial none -serial something' Peter Maydell
2024-02-02 15:36 ` [PULL 08/36] qemu-options.hx: Improve -serial option documentation Peter Maydell
2024-02-02 15:36 ` Peter Maydell [this message]
2024-02-02 15:36 ` [PULL 10/36] tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array Peter Maydell
2024-02-02 15:36 ` [PULL 11/36] target/arm: Reinstate "vfp" property on AArch32 CPUs Peter Maydell
2024-02-02 15:36 ` [PULL 12/36] doc/sphinx/hxtool.py: add optional label argument to SRST directive Peter Maydell
2024-02-02 15:36 ` [PULL 13/36] hw/arm/exynos: Add missing QOM parent for CPU cores Peter Maydell
2024-02-02 15:36 ` [PULL 14/36] hw/arm/exynos: Check for CPU types in machine_run_board_init() Peter Maydell
2024-02-02 15:36 ` [PULL 15/36] hw/arm/highbank: Add missing QOM parent for CPU cores Peter Maydell
2024-02-02 15:36 ` [PULL 16/36] hw/arm/highbank: Check for CPU types in machine_run_board_init() Peter Maydell
2024-02-02 15:36 ` [PULL 17/36] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] Peter Maydell
2024-02-02 15:36 ` [PULL 18/36] hw/arm/musca: " Peter Maydell
2024-02-02 15:36 ` [PULL 19/36] hw/arm/npcm7xx_boards: " Peter Maydell
2024-02-02 15:36 ` [PULL 20/36] hw/arm/vexpress: Check for CPU types in machine_run_board_init() Peter Maydell
2024-02-02 15:36 ` [PULL 21/36] hw/arm/zynq: " Peter Maydell
2024-02-02 15:36 ` [PULL 22/36] pci-host: designware: Limit value range of iATU viewport register Peter Maydell
2024-02-02 15:36 ` [PULL 23/36] hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors Peter Maydell
2024-02-02 15:36 ` [PULL 24/36] hw/arm/z2: " Peter Maydell
2024-02-02 15:36 ` [PULL 25/36] hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports Peter Maydell
2024-02-02 15:36 ` [PULL 26/36] hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints Peter Maydell
2024-02-02 15:36 ` [PULL 27/36] hw/xen/xen-hvm-common.c: " Peter Maydell
2024-02-02 15:36 ` [PULL 28/36] hw/xen: convert stderr prints to error/warn reports Peter Maydell
2024-02-02 15:36 ` [PULL 29/36] hw/net: Add NPCMXXX GMAC device Peter Maydell
2024-02-02 15:36 ` [PULL 30/36] hw/arm: Add GMAC devices to NPCM7XX SoC Peter Maydell
2024-02-02 15:36 ` [PULL 31/36] tests/qtest: Creating qtest for GMAC Module Peter Maydell
2024-02-02 15:36 ` [PULL 32/36] hw/net: GMAC Rx Implementation Peter Maydell
2024-02-02 15:36 ` [PULL 33/36] hw/net: GMAC Tx Implementation Peter Maydell
2024-03-08 13:54 ` Peter Maydell
2024-02-02 15:36 ` [PULL 34/36] tests/qtest: Adding PCS Module test to GMAC Qtest Peter Maydell
2024-02-02 15:36 ` [PULL 35/36] hw/ssi: Implement BCM2835 SPI Controller Peter Maydell
2024-02-02 15:36 ` [PULL 36/36] hw/arm: Connect SPI Controller to BCM2835 Peter Maydell
2024-02-03 13:27 ` [PULL 00/36] target-arm queue Peter Maydell
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