* [PATCH v11 0/3] gdbstub and TCG plugin improvements
@ 2024-02-03 10:11 Akihiko Odaki
2024-02-03 10:11 ` [PATCH v11 1/3] target/riscv: Remove misa_mxl validation Akihiko Odaki
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Akihiko Odaki @ 2024-02-03 10:11 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas, Andrew Jones
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different misa_ext_mask.
V6 -> V7:
Rebased.
V5 -> V6:
Added patch "default-configs: Add TARGET_XML_FILES definition".
Rebased.
V4 -> V5:
Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".
V3 -> V4:
Added patch "gdbstub: Check if gdb_regs is NULL".
V2 -> V3:
Restored patch sets from the previous version.
Rebased to commit 800485762e6564e04e2ab315132d477069562d91.
V1 -> V2:
Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
Added patch "target/riscv: Initialize gdb_core_xml_file only once".
Dropped patch "target/riscv: Remove misa_mxl validation".
Dropped patch "target/riscv: Move misa_mxl_max to class".
Dropped patch "target/riscv: Validate misa_mxl_max only once".
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
Changes in v11:
- Rebased on: https://github.com/alistair23/qemu/tree/riscv-to-apply.next
- Link to v10: https://lore.kernel.org/r/20240128-riscv-v10-0-fdbe593976e9@daynix.com
Changes in v10:
- Dropped patch "hw/riscv: Use misa_mxl instead of misa_mxl_max" due to
invalid assumption that the relevant code is only used for kernel
loading.
- Link to v9: https://lore.kernel.org/r/20240115-riscv-v9-0-ff171e1aedc8@daynix.com
Changes in v9:
- Rebased to commit 977542ded7e6b28d2bc077bcda24568c716e393c.
- Link to v8: https://lore.kernel.org/r/20231218-riscv-v8-0-c9bf2b1582d7@daynix.com
Changes in v8:
- Added a more detailed explanation for patch "hw/riscv: Use misa_mxl
instead of misa_mxl_max". (Alistair Francis)
- Link to v7: https://lore.kernel.org/r/20231213-riscv-v7-0-a760156a337f@daynix.com
---
Akihiko Odaki (3):
target/riscv: Remove misa_mxl validation
target/riscv: Move misa_mxl_max to class
target/riscv: Validate misa_mxl_max only once
target/riscv/cpu.h | 4 +-
hw/riscv/boot.c | 3 +-
target/riscv/cpu.c | 181 ++++++++++++++++++++++++++-------------------
target/riscv/gdbstub.c | 12 ++-
target/riscv/kvm/kvm-cpu.c | 10 +--
target/riscv/machine.c | 7 +-
target/riscv/tcg/tcg-cpu.c | 44 ++---------
target/riscv/translate.c | 3 +-
8 files changed, 133 insertions(+), 131 deletions(-)
---
base-commit: 0c9d286cf791cdda76fd57e4562e2cb18d4a79e2
change-id: 20231213-riscv-fcc9640986cf
Best regards,
--
Akihiko Odaki <akihiko.odaki@daynix.com>
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v11 1/3] target/riscv: Remove misa_mxl validation 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki @ 2024-02-03 10:11 ` Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 2/3] target/riscv: Move misa_mxl_max to class Akihiko Odaki ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Akihiko Odaki @ 2024-02-03 10:11 UTC (permalink / raw) To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones Cc: qemu-riscv, qemu-devel, Akihiko Odaki It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/tcg/tcg-cpu.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index da437975b429..94dca7e446eb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,7 +268,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); @@ -288,11 +288,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max != env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, @@ -908,7 +903,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); - Error *local_err = NULL; if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name = riscv_cpu_get_name(cpu); @@ -917,14 +911,11 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; + Error *local_err = NULL; CPU(cs)->tcg_cflags |= CF_PCREL; -- 2.43.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v11 2/3] target/riscv: Move misa_mxl_max to class 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 1/3] target/riscv: Remove misa_mxl validation Akihiko Odaki @ 2024-02-03 10:11 ` Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 3/3] target/riscv: Validate misa_mxl_max only once Akihiko Odaki ` (2 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Akihiko Odaki @ 2024-02-03 10:11 UTC (permalink / raw) To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones Cc: qemu-riscv, qemu-devel, Akihiko Odaki misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 4 +- hw/riscv/boot.c | 3 +- target/riscv/cpu.c | 160 ++++++++++++++++++++++++--------------------- target/riscv/gdbstub.c | 12 ++-- target/riscv/kvm/kvm-cpu.c | 10 +-- target/riscv/machine.c | 7 +- target/riscv/tcg/tcg-cpu.c | 12 ++-- target/riscv/translate.c | 3 +- 8 files changed, 112 insertions(+), 99 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51381877273e..5c9577f1be7b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,7 +189,6 @@ struct CPUArchState { /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ - uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t xl; /* current xlen */ @@ -471,6 +470,7 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; + uint32_t misa_mxl_max; /* max mxl for this cpu */ }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -783,7 +783,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); bool riscv_cpu_is_vendor(Object *cpu_obj); typedef struct RISCVCPUMultiExtConfig { diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189f0..12f9792245a4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,8 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max == MXL_RV32; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); + return mcc->misa_mxl_max == MXL_RV32; } /* diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88e8cc868144..c9d09d175510 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -301,9 +301,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) { - env->misa_mxl_max = env->misa_mxl = mxl; env->misa_ext_mask = env->misa_ext = ext; } @@ -416,11 +415,7 @@ static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; -#if defined(TARGET_RISCV32) - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#elif defined(TARGET_RISCV64) - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#endif + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), @@ -441,19 +436,17 @@ static void riscv_max_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - RISCVMXL mlx = MXL_RV64; cpu->cfg.mmu = true; cpu->cfg.pmp = true; -#ifdef TARGET_RISCV32 - mlx = MXL_RV32; -#endif - riscv_cpu_set_misa(env, mlx, 0); env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); +#ifdef TARGET_RISCV32 + set_satp_mode_max_supported(cpu, VM_1_10_SV32); +#else + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif #endif } @@ -466,8 +459,6 @@ static void rv64_base_cpu_init(Object *obj) cpu->cfg.mmu = true; cpu->cfg.pmp = true; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -479,8 +470,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - riscv_cpu_set_misa(env, MXL_RV64, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -498,7 +488,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -515,7 +505,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.ext_zfa = true; @@ -546,7 +536,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); env->priv_ver = PRIV_VERSION_1_12_0; /* Enable ISA extensions */ @@ -596,8 +586,6 @@ static void rv128_base_cpu_init(Object *obj) cpu->cfg.mmu = true; cpu->cfg.pmp = true; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -608,7 +596,7 @@ static void rv128_base_cpu_init(Object *obj) static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - riscv_cpu_set_misa(env, MXL_RV64, RVI); + riscv_cpu_set_misa_ext(env, RVI); /* Remove the defaults from the parent class */ RISCV_CPU(obj)->cfg.ext_zicntr = false; @@ -635,8 +623,6 @@ static void rv32_base_cpu_init(Object *obj) cpu->cfg.mmu = true; cpu->cfg.pmp = true; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -648,8 +634,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; - riscv_cpu_set_misa(env, MXL_RV32, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -667,7 +652,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -684,7 +669,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -701,7 +686,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -921,7 +906,7 @@ static void riscv_cpu_reset_hold(Object *obj) mcc->parent_phases.hold(obj); } #ifndef CONFIG_USER_ONLY - env->misa_mxl = env->misa_mxl_max; + env->misa_mxl = mcc->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1298,7 +1283,11 @@ static void riscv_cpu_post_init(Object *obj) static void riscv_cpu_init(Object *obj) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + + env->misa_mxl = mcc->misa_mxl_max; #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, @@ -2276,7 +2265,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { }; #endif -static void riscv_cpu_class_init(ObjectClass *c, void *data) +static void riscv_cpu_common_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); @@ -2309,6 +2298,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } +static void riscv_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); + + mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; +} + static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { @@ -2345,39 +2341,49 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_str; } -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_CPU, \ - .instance_init = initfn \ +#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } -#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init = initfn \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } -#define DEFINE_VENDOR_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_VENDOR_CPU, \ - .instance_init = initfn \ +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_VENDOR_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } -#define DEFINE_BARE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_BARE_CPU, \ - .instance_init = initfn \ +#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_BARE_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } -#define DEFINE_PROFILE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_BARE_CPU, \ - .instance_init = initfn \ +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name = (type_name), \ + .parent = TYPE_RISCV_BARE_CPU, \ + .instance_init = (initfn), \ + .class_init = riscv_cpu_class_init, \ + .class_data = (void *)(misa_mxl_max) \ } static const TypeInfo riscv_cpu_type_infos[] = { @@ -2390,7 +2396,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { .instance_post_init = riscv_cpu_post_init, .abstract = true, .class_size = sizeof(RISCVCPUClass), - .class_init = riscv_cpu_class_init, + .class_init = riscv_cpu_common_class_init, }, { .name = TYPE_RISCV_DYNAMIC_CPU, @@ -2407,25 +2413,27 @@ static const TypeInfo riscv_cpu_type_infos[] = { .parent = TYPE_RISCV_CPU, .abstract = true, }, - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), #endif }; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5ab0abda19a9..0ae0c47df13e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] = { int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; target_ulong tmp; @@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return 0; } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; int length = 0; target_ulong tmp; - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: tmp = (int32_t)ldl_p(mem_buf); length = 4; @@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = 16 << env->misa_mxl_max; + int bitsize = 16 << mcc->misa_mxl_max; int i; #if !defined(CONFIG_USER_ONLY) @@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; if (env->misa_ext & RVD) { @@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) ricsv_gen_dynamic_vector_xml(cs, base_reg), "riscv-vector.xml", 0); } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index a7881de7f9eb..422e4f121c63 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1769,14 +1769,14 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); -static void riscv_host_cpu_init(Object *obj) +static void riscv_host_cpu_class_init(ObjectClass *c, void *data) { - CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); #if defined(TARGET_RISCV32) - env->misa_mxl_max = env->misa_mxl = MXL_RV32; + mcc->misa_mxl_max = MXL_RV32; #elif defined(TARGET_RISCV64) - env->misa_mxl_max = env->misa_mxl = MXL_RV64; + mcc->misa_mxl_max = MXL_RV64; #endif } @@ -1784,7 +1784,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = { { .name = TYPE_RISCV_CPU_HOST, .parent = TYPE_RISCV_CPU, - .instance_init = riscv_host_cpu_init, + .class_init = riscv_host_cpu_class_init, } }; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 72fe2374dc2a..81cf22894e0e 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking = { static bool rv128_needed(void *opaque) { - RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque); - return env->misa_mxl_max == MXL_RV128; + return mcc->misa_mxl_max == MXL_RV128; } static const VMStateDescription vmstate_rv128 = { @@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), - VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 94dca7e446eb..067f1493fea7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -272,10 +272,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPUClass *cc = CPU_CLASS(mcc); - CPURISCVState *env = &cpu->env; /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -426,6 +425,7 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu) */ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; Error *local_err = NULL; @@ -592,7 +592,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -600,7 +600,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { @@ -608,7 +608,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -1307,7 +1307,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef43..20dbc737d775 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1168,6 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu_env(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); uint32_t tb_flags = ctx->base.tb->flags; @@ -1189,7 +1190,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max = env->misa_mxl_max; + ctx->misa_mxl_max = mcc->misa_mxl_max; ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; -- 2.43.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v11 3/3] target/riscv: Validate misa_mxl_max only once 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 1/3] target/riscv: Remove misa_mxl validation Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 2/3] target/riscv: Move misa_mxl_max to class Akihiko Odaki @ 2024-02-03 10:11 ` Akihiko Odaki 2024-02-03 11:08 ` [PATCH v11 0/3] gdbstub and TCG plugin improvements Alex Bennée 2024-02-04 23:42 ` Alistair Francis 4 siblings, 0 replies; 13+ messages in thread From: Akihiko Odaki @ 2024-02-03 10:11 UTC (permalink / raw) To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones Cc: qemu-riscv, qemu-devel, Akihiko Odaki misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c9d09d175510..12a69efe89c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1344,6 +1344,26 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") }; +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc = CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -2303,6 +2323,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 067f1493fea7..e5a60c2e8b60 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc = CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { @@ -911,8 +890,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; Error *local_err = NULL; -- 2.43.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki ` (2 preceding siblings ...) 2024-02-03 10:11 ` [PATCH v11 3/3] target/riscv: Validate misa_mxl_max only once Akihiko Odaki @ 2024-02-03 11:08 ` Alex Bennée 2024-02-03 11:26 ` Akihiko Odaki 2024-02-04 23:42 ` Alistair Francis 4 siblings, 1 reply; 13+ messages in thread From: Alex Bennée @ 2024-02-03 11:08 UTC (permalink / raw) To: Akihiko Odaki Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel Akihiko Odaki <akihiko.odaki@daynix.com> writes: > This series extracts fixes and refactorings that can be applied > independently from "[PATCH v9 00/23] plugins: Allow to read registers". > > The patch "target/riscv: Move MISA limits to class" was replaced with > patch "target/riscv: Move misa_mxl_max to class" since I found instances > may have different misa_ext_mask. As this is re-based on Alistair's riscv-to-apply.next tree I'll wait for this to go through the RiscV trees and then re-base the plugin patches and dropping the merged riscv patches from my tree. In the meantime feel free to review: Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> Date: Mon, 22 Jan 2024 14:55:49 +0000 Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> For: contrib/plugins: extend execlog to track register changes gdbstub: expose api to find registers So I can add this to my maintainer omnibus series for the next PR I send. -- Alex Bennée Virtualisation Tech Lead @ Linaro ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-03 11:08 ` [PATCH v11 0/3] gdbstub and TCG plugin improvements Alex Bennée @ 2024-02-03 11:26 ` Akihiko Odaki 2024-02-03 13:58 ` Alex Bennée 0 siblings, 1 reply; 13+ messages in thread From: Akihiko Odaki @ 2024-02-03 11:26 UTC (permalink / raw) To: Alex Bennée Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel On 2024/02/03 20:08, Alex Bennée wrote: > Akihiko Odaki <akihiko.odaki@daynix.com> writes: > >> This series extracts fixes and refactorings that can be applied >> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >> >> The patch "target/riscv: Move MISA limits to class" was replaced with >> patch "target/riscv: Move misa_mxl_max to class" since I found instances >> may have different misa_ext_mask. > > As this is re-based on Alistair's riscv-to-apply.next tree I'll wait for > this to go through the RiscV trees and then re-base the plugin patches > and dropping the merged riscv patches from my tree. > > In the meantime feel free to review: > > Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> > Date: Mon, 22 Jan 2024 14:55:49 +0000 > Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) > From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> > > For: > > contrib/plugins: extend execlog to track register changes > gdbstub: expose api to find registers > > So I can add this to my maintainer omnibus series for the next PR I > send. I added one trivial comment to: "gdbstub: expose api to find registers" "contrib/plugins: extend execlog to track register changes" depends on "plugins: add an API to read registers". The comments for the patch in the following email are not addressed yet: https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ Please check them out. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-03 11:26 ` Akihiko Odaki @ 2024-02-03 13:58 ` Alex Bennée 2024-02-04 6:54 ` Akihiko Odaki 0 siblings, 1 reply; 13+ messages in thread From: Alex Bennée @ 2024-02-03 13:58 UTC (permalink / raw) To: Akihiko Odaki Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel Akihiko Odaki <akihiko.odaki@daynix.com> writes: > On 2024/02/03 20:08, Alex Bennée wrote: >> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >> >>> This series extracts fixes and refactorings that can be applied >>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>> >>> The patch "target/riscv: Move MISA limits to class" was replaced with >>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>> may have different misa_ext_mask. >> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >> for >> this to go through the RiscV trees and then re-base the plugin patches >> and dropping the merged riscv patches from my tree. >> In the meantime feel free to review: >> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >> Date: Mon, 22 Jan 2024 14:55:49 +0000 >> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >> For: >> contrib/plugins: extend execlog to track register changes >> gdbstub: expose api to find registers >> So I can add this to my maintainer omnibus series for the next PR I >> send. > > I added one trivial comment to: "gdbstub: expose api to find registers" > > "contrib/plugins: extend execlog to track register changes" depends on > "plugins: add an API to read registers". The comments for the patch in > the following email are not addressed yet: > https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ I don't think we need to serialise with the BQL as the structures are per-CPU (and created on vCPU creation). As far as the restructuring we can move it into gdbstub later if there is a need to. At the moment the structure is just housekeeping for plugins. > > Please check them out. -- Alex Bennée Virtualisation Tech Lead @ Linaro ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-03 13:58 ` Alex Bennée @ 2024-02-04 6:54 ` Akihiko Odaki 2024-02-05 9:31 ` Alex Bennée 0 siblings, 1 reply; 13+ messages in thread From: Akihiko Odaki @ 2024-02-04 6:54 UTC (permalink / raw) To: Alex Bennée Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel On 2024/02/03 22:58, Alex Bennée wrote: > Akihiko Odaki <akihiko.odaki@daynix.com> writes: > >> On 2024/02/03 20:08, Alex Bennée wrote: >>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>> >>>> This series extracts fixes and refactorings that can be applied >>>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>>> >>>> The patch "target/riscv: Move MISA limits to class" was replaced with >>>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>>> may have different misa_ext_mask. >>> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >>> for >>> this to go through the RiscV trees and then re-base the plugin patches >>> and dropping the merged riscv patches from my tree. >>> In the meantime feel free to review: >>> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >>> Date: Mon, 22 Jan 2024 14:55:49 +0000 >>> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >>> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >>> For: >>> contrib/plugins: extend execlog to track register changes >>> gdbstub: expose api to find registers >>> So I can add this to my maintainer omnibus series for the next PR I >>> send. >> >> I added one trivial comment to: "gdbstub: expose api to find registers" >> >> "contrib/plugins: extend execlog to track register changes" depends on >> "plugins: add an API to read registers". The comments for the patch in >> the following email are not addressed yet: >> https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ > > I don't think we need to serialise with the BQL as the structures are > per-CPU (and created on vCPU creation). qemu_plugin_get_registers() has vcpu parameter, which can refer to a different vcpu the caller is on (or the caller may not be in a vcpu context at all). > > As far as the restructuring we can move it into gdbstub later if there > is a need to. At the moment the structure is just housekeeping for > plugins. Certainly we can move it later, but adding the code in the plugin infrastructure now won't help in that case. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-04 6:54 ` Akihiko Odaki @ 2024-02-05 9:31 ` Alex Bennée 2024-02-05 10:03 ` Pierrick Bouvier 2024-02-06 8:36 ` Akihiko Odaki 0 siblings, 2 replies; 13+ messages in thread From: Alex Bennée @ 2024-02-05 9:31 UTC (permalink / raw) To: Akihiko Odaki Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel, Pierrick Bouvier Akihiko Odaki <akihiko.odaki@daynix.com> writes: > On 2024/02/03 22:58, Alex Bennée wrote: >> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >> >>> On 2024/02/03 20:08, Alex Bennée wrote: >>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>>> >>>>> This series extracts fixes and refactorings that can be applied >>>>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>>>> >>>>> The patch "target/riscv: Move MISA limits to class" was replaced with >>>>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>>>> may have different misa_ext_mask. >>>> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >>>> for >>>> this to go through the RiscV trees and then re-base the plugin patches >>>> and dropping the merged riscv patches from my tree. >>>> In the meantime feel free to review: >>>> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >>>> Date: Mon, 22 Jan 2024 14:55:49 +0000 >>>> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >>>> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >>>> For: >>>> contrib/plugins: extend execlog to track register changes >>>> gdbstub: expose api to find registers >>>> So I can add this to my maintainer omnibus series for the next PR I >>>> send. >>> >>> I added one trivial comment to: "gdbstub: expose api to find registers" >>> >>> "contrib/plugins: extend execlog to track register changes" depends on >>> "plugins: add an API to read registers". The comments for the patch in >>> the following email are not addressed yet: >>> https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ >> I don't think we need to serialise with the BQL as the structures >> are >> per-CPU (and created on vCPU creation). > > qemu_plugin_get_registers() has vcpu parameter, which can refer to a > different vcpu the caller is on (or the caller may not be in a vcpu > context at all). It should only be called from the current cpu context. We can either assert that or make it implicit like qemu_plugin_insn_disas does. However we will need to ensure current_cpu is set before the vcpu_init callback. Pierrick has had to move these initialisations around for the scoreboard work so they are now run with safe work once the thread starts. > >> As far as the restructuring we can move it into gdbstub later if >> there >> is a need to. At the moment the structure is just housekeeping for >> plugins. > > Certainly we can move it later, but adding the code in the plugin > infrastructure now won't help in that case. -- Alex Bennée Virtualisation Tech Lead @ Linaro ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-05 9:31 ` Alex Bennée @ 2024-02-05 10:03 ` Pierrick Bouvier 2024-02-05 11:20 ` Alex Bennée 2024-02-06 8:36 ` Akihiko Odaki 1 sibling, 1 reply; 13+ messages in thread From: Pierrick Bouvier @ 2024-02-05 10:03 UTC (permalink / raw) To: Alex Bennée, Akihiko Odaki Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel On 2/5/24 13:31, Alex Bennée wrote: > Akihiko Odaki <akihiko.odaki@daynix.com> writes: > >> On 2024/02/03 22:58, Alex Bennée wrote: >>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>> >>>> On 2024/02/03 20:08, Alex Bennée wrote: >>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>>>> >>>>>> This series extracts fixes and refactorings that can be applied >>>>>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>>>>> >>>>>> The patch "target/riscv: Move MISA limits to class" was replaced with >>>>>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>>>>> may have different misa_ext_mask. >>>>> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >>>>> for >>>>> this to go through the RiscV trees and then re-base the plugin patches >>>>> and dropping the merged riscv patches from my tree. >>>>> In the meantime feel free to review: >>>>> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >>>>> Date: Mon, 22 Jan 2024 14:55:49 +0000 >>>>> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >>>>> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >>>>> For: >>>>> contrib/plugins: extend execlog to track register changes >>>>> gdbstub: expose api to find registers >>>>> So I can add this to my maintainer omnibus series for the next PR I >>>>> send. >>>> >>>> I added one trivial comment to: "gdbstub: expose api to find registers" >>>> >>>> "contrib/plugins: extend execlog to track register changes" depends on >>>> "plugins: add an API to read registers". The comments for the patch in >>>> the following email are not addressed yet: >>>> https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ >>> I don't think we need to serialise with the BQL as the structures >>> are >>> per-CPU (and created on vCPU creation). >> >> qemu_plugin_get_registers() has vcpu parameter, which can refer to a >> different vcpu the caller is on (or the caller may not be in a vcpu >> context at all). > > It should only be called from the current cpu context. We can either > assert that or make it implicit like qemu_plugin_insn_disas does. > However we will need to ensure current_cpu is set before the vcpu_init > callback. > > Pierrick has had to move these initialisations around for the scoreboard > work so they are now run with safe work once the thread starts. > As a complement, in the series I'll post, the work is run asynchronously, but not "safe_async", which means it's not under an exclusive section. If you need this guarantee for registers API, it's better to add this. >> >>> As far as the restructuring we can move it into gdbstub later if >>> there >>> is a need to. At the moment the structure is just housekeeping for >>> plugins. >> >> Certainly we can move it later, but adding the code in the plugin >> infrastructure now won't help in that case. > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-05 10:03 ` Pierrick Bouvier @ 2024-02-05 11:20 ` Alex Bennée 0 siblings, 0 replies; 13+ messages in thread From: Alex Bennée @ 2024-02-05 11:20 UTC (permalink / raw) To: Pierrick Bouvier Cc: Akihiko Odaki, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel Pierrick Bouvier <pierrick.bouvier@linaro.org> writes: > On 2/5/24 13:31, Alex Bennée wrote: >> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >> >>> On 2024/02/03 22:58, Alex Bennée wrote: >>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>>> >>>>> On 2024/02/03 20:08, Alex Bennée wrote: >>>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>>>>> >>>>>>> This series extracts fixes and refactorings that can be applied >>>>>>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>>>>>> >>>>>>> The patch "target/riscv: Move MISA limits to class" was replaced with >>>>>>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>>>>>> may have different misa_ext_mask. >>>>>> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >>>>>> for >>>>>> this to go through the RiscV trees and then re-base the plugin patches >>>>>> and dropping the merged riscv patches from my tree. >>>>>> In the meantime feel free to review: >>>>>> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >>>>>> Date: Mon, 22 Jan 2024 14:55:49 +0000 >>>>>> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >>>>>> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >>>>>> For: >>>>>> contrib/plugins: extend execlog to track register changes >>>>>> gdbstub: expose api to find registers >>>>>> So I can add this to my maintainer omnibus series for the next PR I >>>>>> send. >>>>> >>>>> I added one trivial comment to: "gdbstub: expose api to find registers" >>>>> >>>>> "contrib/plugins: extend execlog to track register changes" depends on >>>>> "plugins: add an API to read registers". The comments for the patch in >>>>> the following email are not addressed yet: >>>>> https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ >>>> I don't think we need to serialise with the BQL as the structures >>>> are >>>> per-CPU (and created on vCPU creation). >>> >>> qemu_plugin_get_registers() has vcpu parameter, which can refer to a >>> different vcpu the caller is on (or the caller may not be in a vcpu >>> context at all). >> It should only be called from the current cpu context. We can either >> assert that or make it implicit like qemu_plugin_insn_disas does. >> However we will need to ensure current_cpu is set before the vcpu_init >> callback. >> Pierrick has had to move these initialisations around for the >> scoreboard >> work so they are now run with safe work once the thread starts. >> > > As a complement, in the series I'll post, the work is run > asynchronously, but not "safe_async", which means it's not under an > exclusive section. > > If you need this guarantee for registers API, it's better to add this. We don't. We just want to ensure they line up and are not cross-vCPU. > >>> >>>> As far as the restructuring we can move it into gdbstub later if >>>> there >>>> is a need to. At the moment the structure is just housekeeping for >>>> plugins. >>> >>> Certainly we can move it later, but adding the code in the plugin >>> infrastructure now won't help in that case. >> -- Alex Bennée Virtualisation Tech Lead @ Linaro ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-05 9:31 ` Alex Bennée 2024-02-05 10:03 ` Pierrick Bouvier @ 2024-02-06 8:36 ` Akihiko Odaki 1 sibling, 0 replies; 13+ messages in thread From: Akihiko Odaki @ 2024-02-06 8:36 UTC (permalink / raw) To: Alex Bennée Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel, Pierrick Bouvier On 2024/02/05 18:31, Alex Bennée wrote: > Akihiko Odaki <akihiko.odaki@daynix.com> writes: > >> On 2024/02/03 22:58, Alex Bennée wrote: >>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>> >>>> On 2024/02/03 20:08, Alex Bennée wrote: >>>>> Akihiko Odaki <akihiko.odaki@daynix.com> writes: >>>>> >>>>>> This series extracts fixes and refactorings that can be applied >>>>>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>>>>> >>>>>> The patch "target/riscv: Move MISA limits to class" was replaced with >>>>>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>>>>> may have different misa_ext_mask. >>>>> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >>>>> for >>>>> this to go through the RiscV trees and then re-base the plugin patches >>>>> and dropping the merged riscv patches from my tree. >>>>> In the meantime feel free to review: >>>>> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >>>>> Date: Mon, 22 Jan 2024 14:55:49 +0000 >>>>> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (pre-PR?) >>>>> From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org> >>>>> For: >>>>> contrib/plugins: extend execlog to track register changes >>>>> gdbstub: expose api to find registers >>>>> So I can add this to my maintainer omnibus series for the next PR I >>>>> send. >>>> >>>> I added one trivial comment to: "gdbstub: expose api to find registers" >>>> >>>> "contrib/plugins: extend execlog to track register changes" depends on >>>> "plugins: add an API to read registers". The comments for the patch in >>>> the following email are not addressed yet: >>>> https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.com/ >>> I don't think we need to serialise with the BQL as the structures >>> are >>> per-CPU (and created on vCPU creation). >> >> qemu_plugin_get_registers() has vcpu parameter, which can refer to a >> different vcpu the caller is on (or the caller may not be in a vcpu >> context at all). > > It should only be called from the current cpu context. We can either > assert that or make it implicit like qemu_plugin_insn_disas does. > However we will need to ensure current_cpu is set before the vcpu_init > callback. Then that should be documented and the vcpu_index parameter should be deleted. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki ` (3 preceding siblings ...) 2024-02-03 11:08 ` [PATCH v11 0/3] gdbstub and TCG plugin improvements Alex Bennée @ 2024-02-04 23:42 ` Alistair Francis 4 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2024-02-04 23:42 UTC (permalink / raw) To: Akihiko Odaki Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée, Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé, Fabiano Rosas, Andrew Jones, qemu-riscv, qemu-devel On Sat, Feb 3, 2024 at 8:12 PM Akihiko Odaki <akihiko.odaki@daynix.com> wrote: > > This series extracts fixes and refactorings that can be applied > independently from "[PATCH v9 00/23] plugins: Allow to read registers". > > The patch "target/riscv: Move MISA limits to class" was replaced with > patch "target/riscv: Move misa_mxl_max to class" since I found instances > may have different misa_ext_mask. > > V6 -> V7: > Rebased. > > V5 -> V6: > Added patch "default-configs: Add TARGET_XML_FILES definition". > Rebased. > > V4 -> V5: > Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max". > > V3 -> V4: > Added patch "gdbstub: Check if gdb_regs is NULL". > > V2 -> V3: > Restored patch sets from the previous version. > Rebased to commit 800485762e6564e04e2ab315132d477069562d91. > > V1 -> V2: > Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64". > Added patch "target/riscv: Initialize gdb_core_xml_file only once". > Dropped patch "target/riscv: Remove misa_mxl validation". > Dropped patch "target/riscv: Move misa_mxl_max to class". > Dropped patch "target/riscv: Validate misa_mxl_max only once". > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > --- > Changes in v11: > - Rebased on: https://github.com/alistair23/qemu/tree/riscv-to-apply.next > - Link to v10: https://lore.kernel.org/r/20240128-riscv-v10-0-fdbe593976e9@daynix.com > > Changes in v10: > - Dropped patch "hw/riscv: Use misa_mxl instead of misa_mxl_max" due to > invalid assumption that the relevant code is only used for kernel > loading. > - Link to v9: https://lore.kernel.org/r/20240115-riscv-v9-0-ff171e1aedc8@daynix.com > > Changes in v9: > - Rebased to commit 977542ded7e6b28d2bc077bcda24568c716e393c. > - Link to v8: https://lore.kernel.org/r/20231218-riscv-v8-0-c9bf2b1582d7@daynix.com > > Changes in v8: > - Added a more detailed explanation for patch "hw/riscv: Use misa_mxl > instead of misa_mxl_max". (Alistair Francis) > - Link to v7: https://lore.kernel.org/r/20231213-riscv-v7-0-a760156a337f@daynix.com > > --- > Akihiko Odaki (3): > target/riscv: Remove misa_mxl validation > target/riscv: Move misa_mxl_max to class > target/riscv: Validate misa_mxl_max only once Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 4 +- > hw/riscv/boot.c | 3 +- > target/riscv/cpu.c | 181 ++++++++++++++++++++++++++------------------- > target/riscv/gdbstub.c | 12 ++- > target/riscv/kvm/kvm-cpu.c | 10 +-- > target/riscv/machine.c | 7 +- > target/riscv/tcg/tcg-cpu.c | 44 ++--------- > target/riscv/translate.c | 3 +- > 8 files changed, 133 insertions(+), 131 deletions(-) > --- > base-commit: 0c9d286cf791cdda76fd57e4562e2cb18d4a79e2 > change-id: 20231213-riscv-fcc9640986cf > > Best regards, > -- > Akihiko Odaki <akihiko.odaki@daynix.com> > > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-02-06 8:37 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-02-03 10:11 [PATCH v11 0/3] gdbstub and TCG plugin improvements Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 1/3] target/riscv: Remove misa_mxl validation Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 2/3] target/riscv: Move misa_mxl_max to class Akihiko Odaki 2024-02-03 10:11 ` [PATCH v11 3/3] target/riscv: Validate misa_mxl_max only once Akihiko Odaki 2024-02-03 11:08 ` [PATCH v11 0/3] gdbstub and TCG plugin improvements Alex Bennée 2024-02-03 11:26 ` Akihiko Odaki 2024-02-03 13:58 ` Alex Bennée 2024-02-04 6:54 ` Akihiko Odaki 2024-02-05 9:31 ` Alex Bennée 2024-02-05 10:03 ` Pierrick Bouvier 2024-02-05 11:20 ` Alex Bennée 2024-02-06 8:36 ` Akihiko Odaki 2024-02-04 23:42 ` Alistair Francis
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