From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 12/39] target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
Date: Mon, 5 Feb 2024 07:40:25 +1000 [thread overview]
Message-ID: <20240204214052.5639-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240204214052.5639-1-richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 74 ++++++++++++++++++-----------------------
1 file changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index f886190f88..d7d5ff4300 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5129,46 +5129,44 @@ undef:
static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv fpsr;
+ int imm = 0;
- c->v2 = tcg_constant_i32(0);
/* TODO: Raise BSUN exception. */
fpsr = tcg_temp_new();
gen_load_fcr(s, fpsr, M68K_FPSR);
+ c->v1 = fpsr;
+
switch (cond) {
case 0: /* False */
case 16: /* Signaling False */
- c->v1 = c->v2;
c->tcond = TCG_COND_NEVER;
break;
case 1: /* EQual Z */
case 17: /* Signaling EQual Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTNE;
break;
case 2: /* Ordered Greater Than !(A || Z || N) */
case 18: /* Greater Than !(A || Z || N) */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr,
- FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 3: /* Ordered Greater than or Equal Z || !(A || N) */
case 19: /* Greater than or Equal Z || !(A || N) */
c->v1 = tcg_temp_new();
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
- tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
tcg_gen_or_i32(c->v1, c->v1, fpsr);
tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 4: /* Ordered Less Than !(!N || A || Z); */
case 20: /* Less Than !(!N || A || Z); */
c->v1 = tcg_temp_new();
tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 5: /* Ordered Less than or Equal Z || (N && !A) */
case 21: /* Less than or Equal Z || (N && !A) */
@@ -5176,49 +5174,45 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 6: /* Ordered Greater or Less than !(A || Z) */
case 22: /* Greater or Less than !(A || Z) */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 7: /* Ordered !A */
case 23: /* Greater, Less or Equal !A */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_A;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 8: /* Unordered A */
case 24: /* Not Greater, Less or Equal A */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A;
+ c->tcond = TCG_COND_TSTNE;
break;
case 9: /* Unordered or Equal A || Z */
case 25: /* Not Greater or Less then A || Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTNE;
break;
case 10: /* Unordered or Greater Than A || !(N || Z)) */
case 26: /* Not Less or Equal A || !(N || Z)) */
c->v1 = tcg_temp_new();
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
- tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
tcg_gen_or_i32(c->v1, c->v1, fpsr);
tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 11: /* Unordered or Greater or Equal A || Z || !N */
case 27: /* Not Less Than A || Z || !N */
c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 12: /* Unordered or Less Than A || (N && !Z) */
case 28: /* Not Greater than or Equal A || (N && !Z) */
@@ -5226,27 +5220,25 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
- tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 13: /* Unordered or Less or Equal A || Z || N */
case 29: /* Not Greater Than A || Z || N */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
- c->tcond = TCG_COND_NE;
+ imm = FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N;
+ c->tcond = TCG_COND_TSTNE;
break;
case 14: /* Not Equal !Z */
case 30: /* Signaling Not Equal !Z */
- c->v1 = tcg_temp_new();
- tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
- c->tcond = TCG_COND_EQ;
+ imm = FPSR_CC_Z;
+ c->tcond = TCG_COND_TSTEQ;
break;
case 15: /* True */
case 31: /* Signaling True */
- c->v1 = c->v2;
c->tcond = TCG_COND_ALWAYS;
break;
}
+ c->v2 = tcg_constant_i32(imm);
}
static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
--
2.34.1
next prev parent reply other threads:[~2024-02-04 21:41 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-04 21:40 [PULL 00/39] tcg patch queue Richard Henderson
2024-02-04 21:40 ` [PULL 01/39] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 02/39] tcg: Introduce TCG_TARGET_HAS_tst Richard Henderson
2024-02-04 21:40 ` [PULL 03/39] tcg/optimize: Split out arg_is_const_val Richard Henderson
2024-02-04 21:40 ` [PULL 04/39] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2024-02-04 21:40 ` [PULL 05/39] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2024-02-04 21:40 ` [PULL 06/39] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 07/39] tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported Richard Henderson
2024-02-04 21:40 ` [PULL 08/39] target/alpha: Pass immediate value to gen_bcond_internal() Richard Henderson
2024-02-04 21:40 ` [PULL 09/39] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2024-02-04 21:40 ` [PULL 10/39] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Richard Henderson
2024-02-04 21:40 ` [PULL 11/39] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2024-02-04 21:40 ` Richard Henderson [this message]
2024-02-04 21:40 ` [PULL 13/39] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc Richard Henderson
2024-02-04 21:40 ` [PULL 14/39] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} Richard Henderson
2024-02-04 21:40 ` [PULL 15/39] target/s390x: Improve general case of disas_jcc Richard Henderson
2024-02-04 21:40 ` [PULL 16/39] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2024-02-04 21:40 ` [PULL 17/39] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 18/39] tcg/aarch64: Massage tcg_out_brcond() Richard Henderson
2024-02-04 21:40 ` [PULL 19/39] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2024-02-04 21:40 ` [PULL 20/39] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2024-02-04 21:40 ` [PULL 21/39] tcg/arm: Split out tcg_out_cmp() Richard Henderson
2024-02-04 21:40 ` [PULL 22/39] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 23/39] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2024-02-04 21:40 ` [PULL 24/39] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2024-02-04 21:40 ` [PULL 25/39] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 26/39] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2024-02-04 21:40 ` [PULL 27/39] tcg/i386: Use TEST r,r to test 8/16/32 bits Richard Henderson
2024-02-04 21:40 ` [PULL 28/39] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2024-02-04 21:40 ` [PULL 29/39] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2024-02-04 21:40 ` [PULL 30/39] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 31/39] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2024-02-04 21:40 ` [PULL 32/39] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2024-02-04 21:40 ` [PULL 33/39] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2024-02-04 21:40 ` [PULL 34/39] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2024-02-04 21:40 ` [PULL 35/39] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 36/39] tcg/s390x: Split constraint A into J+U Richard Henderson
2024-02-04 21:40 ` [PULL 37/39] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2024-02-04 21:40 ` [PULL 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 39/39] tcg/tci: " Richard Henderson
2024-02-05 12:59 ` [PULL 00/39] tcg patch queue Peter Maydell
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