From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 25/39] tcg/i386: Support TCG_COND_TST{EQ,NE}
Date: Mon, 5 Feb 2024 07:40:38 +1000 [thread overview]
Message-ID: <20240204214052.5639-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240204214052.5639-1-richard.henderson@linaro.org>
Merge tcg_out_testi into tcg_out_cmp and adjust the two uses.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 95 ++++++++++++++++++++++++---------------
2 files changed, 60 insertions(+), 37 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 1dd917a680..a10d4e1fce 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -198,7 +198,7 @@ typedef enum {
#define TCG_TARGET_HAS_qemu_ldst_i128 \
(TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
-#define TCG_TARGET_HAS_tst 0
+#define TCG_TARGET_HAS_tst 1
/* We do not support older SSE systems, only beginning with AVX1. */
#define TCG_TARGET_HAS_v64 have_avx1
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 02718a02d8..f2414177bd 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -506,6 +506,8 @@ static const uint8_t tcg_cond_to_jcc[] = {
[TCG_COND_GEU] = JCC_JAE,
[TCG_COND_LEU] = JCC_JBE,
[TCG_COND_GTU] = JCC_JA,
+ [TCG_COND_TSTEQ] = JCC_JE,
+ [TCG_COND_TSTNE] = JCC_JNE,
};
#if TCG_TARGET_REG_BITS == 64
@@ -1452,17 +1454,49 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small)
static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1,
TCGArg arg2, int const_arg2, int rexw)
{
- if (const_arg2) {
- if (arg2 == 0) {
- /* test r, r */
+ int jz;
+
+ if (!is_tst_cond(cond)) {
+ if (!const_arg2) {
+ tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
+ } else if (arg2 == 0) {
tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1);
} else {
+ tcg_debug_assert(!rexw || arg2 == (int32_t)arg2);
tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0);
}
- } else {
- tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
+ return tcg_cond_to_jcc[cond];
}
- return tcg_cond_to_jcc[cond];
+
+ jz = tcg_cond_to_jcc[cond];
+
+ if (!const_arg2) {
+ tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2);
+ return jz;
+ }
+
+ if (arg2 <= 0xff && (TCG_TARGET_REG_BITS == 64 || arg1 < 4)) {
+ tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, arg1);
+ tcg_out8(s, arg2);
+ return jz;
+ }
+
+ if ((arg2 & ~0xff00) == 0 && arg1 < 4) {
+ tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, arg1 + 4);
+ tcg_out8(s, arg2 >> 8);
+ return jz;
+ }
+
+ if (rexw) {
+ if (arg2 == (uint32_t)arg2) {
+ rexw = 0;
+ } else {
+ tcg_debug_assert(arg2 == (int32_t)arg2);
+ }
+ }
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_TESTi, arg1);
+ tcg_out32(s, arg2);
+ return jz;
}
static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond,
@@ -1479,18 +1513,21 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
{
TCGLabel *label_next = gen_new_label();
TCGLabel *label_this = arg_label(args[5]);
+ TCGCond cond = args[4];
- switch(args[4]) {
+ switch (cond) {
case TCG_COND_EQ:
- tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2],
- label_next, 1);
- tcg_out_brcond(s, 0, TCG_COND_EQ, args[1], args[3], const_args[3],
+ case TCG_COND_TSTEQ:
+ tcg_out_brcond(s, 0, tcg_invert_cond(cond),
+ args[0], args[2], const_args[2], label_next, 1);
+ tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3],
label_this, small);
break;
case TCG_COND_NE:
- tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2],
+ case TCG_COND_TSTNE:
+ tcg_out_brcond(s, 0, cond, args[0], args[2], const_args[2],
label_this, small);
- tcg_out_brcond(s, 0, TCG_COND_NE, args[1], args[3], const_args[3],
+ tcg_out_brcond(s, 0, cond, args[1], args[3], const_args[3],
label_this, small);
break;
case TCG_COND_LT:
@@ -1827,23 +1864,6 @@ static void tcg_out_nopn(TCGContext *s, int n)
tcg_out8(s, 0x90);
}
-/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */
-static void __attribute__((unused))
-tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i)
-{
- /*
- * This is used for testing alignment, so we can usually use testb.
- * For i686, we have to use testl for %esi/%edi.
- */
- if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) {
- tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r);
- tcg_out8(s, i);
- } else {
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r);
- tcg_out32(s, i);
- }
-}
-
typedef struct {
TCGReg base;
int index;
@@ -2104,16 +2124,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
offsetof(CPUTLBEntry, addend));
} else if (a_mask) {
- ldst = new_ldst_label(s);
+ int jcc;
+ ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
ldst->addrlo_reg = addrlo;
ldst->addrhi_reg = addrhi;
- tcg_out_testi(s, addrlo, a_mask);
/* jne slow_path */
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addrlo, a_mask, true, false);
+ tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0);
ldst->label_ptr[0] = s->code_ptr;
s->code_ptr += 4;
}
@@ -2259,9 +2280,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
} else {
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
+ int jcc;
- tcg_out_testi(s, h.base, 15);
- tcg_out_jxx(s, JCC_JNE, l1, true);
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false);
+ tcg_out_jxx(s, jcc, l1, true);
tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg,
TCG_TMP_VEC, 0,
@@ -2387,9 +2409,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
} else {
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
+ int jcc;
- tcg_out_testi(s, h.base, 15);
- tcg_out_jxx(s, JCC_JNE, l1, true);
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, h.base, 15, true, false);
+ tcg_out_jxx(s, jcc, l1, true);
tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg,
TCG_TMP_VEC, 0,
--
2.34.1
next prev parent reply other threads:[~2024-02-04 21:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-04 21:40 [PULL 00/39] tcg patch queue Richard Henderson
2024-02-04 21:40 ` [PULL 01/39] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 02/39] tcg: Introduce TCG_TARGET_HAS_tst Richard Henderson
2024-02-04 21:40 ` [PULL 03/39] tcg/optimize: Split out arg_is_const_val Richard Henderson
2024-02-04 21:40 ` [PULL 04/39] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2024-02-04 21:40 ` [PULL 05/39] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2024-02-04 21:40 ` [PULL 06/39] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 07/39] tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported Richard Henderson
2024-02-04 21:40 ` [PULL 08/39] target/alpha: Pass immediate value to gen_bcond_internal() Richard Henderson
2024-02-04 21:40 ` [PULL 09/39] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2024-02-04 21:40 ` [PULL 10/39] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} Richard Henderson
2024-02-04 21:40 ` [PULL 11/39] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2024-02-04 21:40 ` [PULL 12/39] target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond Richard Henderson
2024-02-04 21:40 ` [PULL 13/39] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc Richard Henderson
2024-02-04 21:40 ` [PULL 14/39] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} Richard Henderson
2024-02-04 21:40 ` [PULL 15/39] target/s390x: Improve general case of disas_jcc Richard Henderson
2024-02-04 21:40 ` [PULL 16/39] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2024-02-04 21:40 ` [PULL 17/39] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 18/39] tcg/aarch64: Massage tcg_out_brcond() Richard Henderson
2024-02-04 21:40 ` [PULL 19/39] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2024-02-04 21:40 ` [PULL 20/39] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2024-02-04 21:40 ` [PULL 21/39] tcg/arm: Split out tcg_out_cmp() Richard Henderson
2024-02-04 21:40 ` [PULL 22/39] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 23/39] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2024-02-04 21:40 ` [PULL 24/39] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2024-02-04 21:40 ` Richard Henderson [this message]
2024-02-04 21:40 ` [PULL 26/39] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2024-02-04 21:40 ` [PULL 27/39] tcg/i386: Use TEST r,r to test 8/16/32 bits Richard Henderson
2024-02-04 21:40 ` [PULL 28/39] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2024-02-04 21:40 ` [PULL 29/39] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2024-02-04 21:40 ` [PULL 30/39] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 31/39] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2024-02-04 21:40 ` [PULL 32/39] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Richard Henderson
2024-02-04 21:40 ` [PULL 33/39] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2024-02-04 21:40 ` [PULL 34/39] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2024-02-04 21:40 ` [PULL 35/39] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 36/39] tcg/s390x: Split constraint A into J+U Richard Henderson
2024-02-04 21:40 ` [PULL 37/39] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2024-02-04 21:40 ` [PULL 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-04 21:40 ` [PULL 39/39] tcg/tci: " Richard Henderson
2024-02-05 12:59 ` [PULL 00/39] tcg patch queue Peter Maydell
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