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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id j3-20020a5d4523000000b0033b17880eacsm2473722wra.56.2024.02.06.08.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 08:29:27 -0800 (PST) Date: Tue, 6 Feb 2024 17:29:26 +0100 From: Andrew Jones To: Vadim Shakirov Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org Subject: Re: [PATCH v4] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit Message-ID: <20240206-f53ed33cab0ae364e10d9b6b@orel> References: <20240202113919.18236-1-vadim.shakirov@syntacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240202113919.18236-1-vadim.shakirov@syntacore.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Feb 02, 2024 at 02:39:19PM +0300, Vadim Shakirov wrote: > mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit > by privileged spec > > Signed-off-by: Vadim Shakirov You should have added my and Alistair's tags when reposting. And you should CC previous reviewers. Anyway, here's mine again Reviewed-by: Andrew Jones drew > --- > target/riscv/cpu.h | 8 ++++---- > target/riscv/machine.c | 16 ++++++++-------- > 2 files changed, 12 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5138187727..cf1867a6e2 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -271,7 +271,7 @@ struct CPUArchState { > target_ulong hstatus; > target_ulong hedeleg; > uint64_t hideleg; > - target_ulong hcounteren; > + uint32_t hcounteren; > target_ulong htval; > target_ulong htinst; > target_ulong hgatp; > @@ -334,10 +334,10 @@ struct CPUArchState { > */ > bool two_stage_indirect_lookup; > > - target_ulong scounteren; > - target_ulong mcounteren; > + uint32_t scounteren; > + uint32_t mcounteren; > > - target_ulong mcountinhibit; > + uint32_t mcountinhibit; > > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 72fe2374dc..a4d47ec17e 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -79,14 +79,14 @@ static bool hyper_needed(void *opaque) > > static const VMStateDescription vmstate_hyper = { > .name = "cpu/hyper", > - .version_id = 3, > - .minimum_version_id = 3, > + .version_id = 4, > + .minimum_version_id = 4, > .needed = hyper_needed, > .fields = (const VMStateField[]) { > VMSTATE_UINTTL(env.hstatus, RISCVCPU), > VMSTATE_UINTTL(env.hedeleg, RISCVCPU), > VMSTATE_UINT64(env.hideleg, RISCVCPU), > - VMSTATE_UINTTL(env.hcounteren, RISCVCPU), > + VMSTATE_UINT32(env.hcounteren, RISCVCPU), > VMSTATE_UINTTL(env.htval, RISCVCPU), > VMSTATE_UINTTL(env.htinst, RISCVCPU), > VMSTATE_UINTTL(env.hgatp, RISCVCPU), > @@ -354,8 +354,8 @@ static const VMStateDescription vmstate_jvt = { > > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > - .version_id = 9, > - .minimum_version_id = 9, > + .version_id = 10, > + .minimum_version_id = 10, > .post_load = riscv_cpu_post_load, > .fields = (const VMStateField[]) { > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > @@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINTTL(env.mtval, RISCVCPU), > VMSTATE_UINTTL(env.miselect, RISCVCPU), > VMSTATE_UINTTL(env.siselect, RISCVCPU), > - VMSTATE_UINTTL(env.scounteren, RISCVCPU), > - VMSTATE_UINTTL(env.mcounteren, RISCVCPU), > - VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), > + VMSTATE_UINT32(env.scounteren, RISCVCPU), > + VMSTATE_UINT32(env.mcounteren, RISCVCPU), > + VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), > VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, > vmstate_pmu_ctr_state, PMUCTRState), > VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), > -- > 2.34.1 > >