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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, gustavo.romero@linaro.org
Subject: [PATCH v2 3/6] target/arm: Adjust and validate mtedesc sizem1
Date: Tue,  6 Feb 2024 13:05:24 +1000	[thread overview]
Message-ID: <20240206030527.169147-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240206030527.169147-1-richard.henderson@linaro.org>

When we added SVE_MTEDESC_SHIFT, we effectively limited the
maximum size of MTEDESC.  Adjust SIZEM1 to consume the remaining
bits (32 - 10 - 5 - 12 == 5).  Assert that the data to be stored
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/internals.h         | 2 +-
 target/arm/tcg/translate-sve.c | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index fc337fe40e..50bff44549 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1278,7 +1278,7 @@ FIELD(MTEDESC, TBI,   4, 2)
 FIELD(MTEDESC, TCMA,  6, 2)
 FIELD(MTEDESC, WRITE, 8, 1)
 FIELD(MTEDESC, ALIGN, 9, 3)
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12)  /* size - 1 */
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12)  /* size - 1 */
 
 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index f50a426c98..2628ac2840 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4443,17 +4443,18 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
 {
     unsigned vsz = vec_full_reg_size(s);
     TCGv_ptr t_pg;
+    uint32_t sizem1;
     int desc = 0;
 
     assert(mte_n >= 1 && mte_n <= 4);
+    sizem1 = (mte_n << dtype_msz(dtype)) - 1;
+    assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
     if (s->mte_active[0]) {
-        int msz = dtype_msz(dtype);
-
         desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
         desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
         desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
+        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
         desc <<= SVE_MTEDESC_SHIFT;
     } else {
         addr = clean_data_tbi(s, addr);
-- 
2.34.1



  parent reply	other threads:[~2024-02-06  3:08 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-06  3:05 [PATCH v2 0/6] target/arm: assorted mte fixes Richard Henderson
2024-02-06  3:05 ` [PATCH v2 1/6] linux-user/aarch64: Extend PR_SET_TAGGED_ADDR_CTRL for FEAT_MTE3 Richard Henderson
2024-02-06 14:23   ` Peter Maydell
2024-02-07  0:31     ` Richard Henderson
2024-02-07  2:10     ` Richard Henderson
2024-02-06 15:18   ` Gustavo Romero
2024-02-06  3:05 ` [PATCH v2 2/6] target/arm: Fix nregs computation in do_ld_zpa Richard Henderson
2024-02-06 14:46   ` Peter Maydell
2024-02-07  0:42     ` Richard Henderson
2024-02-06  3:05 ` Richard Henderson [this message]
2024-02-06 14:49   ` [PATCH v2 3/6] target/arm: Adjust and validate mtedesc sizem1 Peter Maydell
2024-02-06  3:05 ` [PATCH v2 4/6] target/arm: Split out make_svemte_desc Richard Henderson
2024-02-06 14:52   ` Peter Maydell
2024-02-06  3:05 ` [PATCH v2 5/6] target/arm: Handle mte in do_ldrq, do_ldro Richard Henderson
2024-02-06 14:53   ` Peter Maydell
2024-02-06  3:05 ` [PATCH v2 6/6] target/arm: Fix SVE/SME gross MTE suppression checks Richard Henderson
2024-02-06 14:54   ` Peter Maydell
2024-02-06 14:54 ` [PATCH v2 0/6] target/arm: assorted mte fixes Peter Maydell
2024-02-06 20:10   ` Richard Henderson
2024-02-06 15:17 ` Gustavo Romero

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