[RFC PATCH 11/11] target/mips: Remove I6500 CPU definition

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

I6500 support is incomplete as it lacks SAAR (Special Address
Access Register) and DSPRAM (Data Scratch Pad RAM) features.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 docs/about/removed-features.rst |  5 +++++
 tests/qtest/machine-none-test.c |  2 +-
 target/mips/cpu-defs.c.inc      | 40 ---------------------------------
 3 files changed, 6 insertions(+), 41 deletions(-)

diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index 54081a6c19..d61b4c92dd 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -727,6 +727,11 @@ x86 ``Icelake-Client`` CPU (removed in 7.1)
 There isn't ever Icelake Client CPU, it is some wrong and imaginary one.
 Use ``Icelake-Server`` instead.
 
+MIPS I6500 CPU (removed in 9.0)
+'''''''''''''''''''''''''''''''
+
+The I6500 support was never fully contributed.
+
 System accelerators
 -------------------
 
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
index 31cc0bfb01..b653a0dd5c 100644
--- a/tests/qtest/machine-none-test.c
+++ b/tests/qtest/machine-none-test.c
@@ -37,7 +37,7 @@ static struct arch2cpu cpus_map[] = {
     { "mips", "4Kc" },
     { "mipsel", "I7200" },
     { "mips64", "20Kc" },
-    { "mips64el", "I6500" },
+    { "mips64el", "I6400" },
     { "nios2", "FIXME" },
     { "or1k", "or1200" },
     { "ppc", "604" },
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index fbf787d8ce..ce2c01cbfa 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -778,46 +778,6 @@ const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R6,
         .mmu_type = MMU_TYPE_R4000,
     },
-    {
-        .name = "I6500",
-        .CP0_PRid = 0x1B000,
-        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
-                       (MMU_TYPE_R4000 << CP0C0_MT),
-        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
-                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
-                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
-                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
-        .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
-                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
-                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
-                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
-        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
-                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
-        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
-                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
-        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
-                                  (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
-        .CP0_LLAddr_rw_bitmask = 0,
-        .CP0_LLAddr_shift = 0,
-        .SYNCI_Step = 64,
-        .CCRes = 2,
-        .CP0_Status_rw_bitmask = 0x30D8FFFF,
-        .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
-                         (1U << CP0PG_RIE),
-        .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
-        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
-        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
-                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
-                    (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
-        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
-        .CP1_fcr31_rw_bitmask = 0x0103FFFF,
-        .MSAIR = 0x03 << MSAIR_ProcID,
-        .SEGBITS = 48,
-        .PABITS = 48,
-        .insn_flags = CPU_MIPS64R6,
-        .mmu_type = MMU_TYPE_R4000,
-    },
     {
         .name = "Loongson-2E",
         .CP0_PRid = 0x6302,
-- 
2.41.0