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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id jr6-20020a05600c560600b0041079d336c7sm12069464wmb.39.2024.02.13.07.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 07:33:21 -0800 (PST) Date: Tue, 13 Feb 2024 16:33:21 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH RFC] target: riscv: Add Svvptc extension support Message-ID: <20240213-87d669a3bd421a1b2bc30fc2@orel> References: <20240213145308.869874-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240213145308.869874-1-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote: > The Svvptc extension describes a uarch that does not cache invalid TLB > entries: that's the case for qemu so there is nothing particular to > implement other than the introduction of this extension, which is done > here. > > Signed-off-by: Alexandre Ghiti > --- > > That's an RFC since the extension has not been ratified yet. Hi Alex, No need for the RFC tag. You can add not-yet-ratified extension support to QEMU as long as the CPU property is off by default (as you've done) and you add it to the riscv_cpu_experimental_exts[] array with an "x-" prefix on its property name. Thanks, drew > > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1b8d001d23..4beb5d0350 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -1467,6 +1468,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), > + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, false), > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 833bf58217..c973693b6e 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -77,6 +77,7 @@ struct RISCVCPUConfig { > bool ext_svinval; > bool ext_svnapot; > bool ext_svpbmt; > + bool ext_svvptc; > bool ext_zdinx; > bool ext_zaamo; > bool ext_zacas; > -- > 2.39.2 > >