From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Lucas Mateus Castro" <lucas.castro@eldorado.org.br>,
qemu-devel@nongnu.org, qemu-stable@nongnu.org,
"Joel Stanley" <joel@jms.id.au>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Subject: [PATCH] target/ppc: Fix lxv/stxv MSR facility check
Date: Tue, 13 Feb 2024 18:39:33 +1000 [thread overview]
Message-ID: <20240213083933.718881-1-npiggin@gmail.com> (raw)
The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.
This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would result in wrong registers
being loaded, potentially overwriting live values and/or exposing
stale ones.
Cc: qemu-stable@nongnu.org
Reported-by: Joel Stanley <joel@jms.id.au>
Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to decodtree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1769
Tested-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/translate/vsx-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6db87ab336..0266f09119 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2268,7 +2268,7 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
{
- if (paired || a->rt >= 32) {
+ if (paired || a->rt < 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
--
2.42.0
next reply other threads:[~2024-02-13 8:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 8:39 Nicholas Piggin [this message]
2024-02-13 9:18 ` [PATCH] target/ppc: Fix lxv/stxv MSR facility check Harsh Prateek Bora
2024-02-14 7:35 ` Cédric Le Goater
2024-09-09 23:06 ` Fabiano Rosas
2024-09-13 4:40 ` Harsh Prateek Bora
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