From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Shiyang Ruan <ruansy.fnst@fujitsu.com>
Cc: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
<dan.j.williams@intel.com>
Subject: Re: [RFC PATCH 1/2] hw/cxl/type3: add missing flag bit for GMER
Date: Tue, 13 Feb 2024 16:27:23 +0000 [thread overview]
Message-ID: <20240213162723.0000514f@Huawei.com> (raw)
In-Reply-To: <20240209115417.724638-2-ruansy.fnst@fujitsu.com>
On Fri, 9 Feb 2024 19:54:11 +0800
Shiyang Ruan <ruansy.fnst@fujitsu.com> wrote:
> The "Volatile" should be set if current device is a volatile memory.
> Per CXL Spec r3.0 8.2.9.2.1.1, Table 8-43.
Whilst true, we haven't previously adjusted the injected record
to conform to the device. I don't think there is anything preventing
you setting this bit in the dpa fields whilst injecting.
I'm not against filling this in automatically but we should be
masking the relevant bits out of what is injected and filling it in based
on the dpa that is provided and which memory that falls within.
>
> Signed-off-by: Shiyang Ruan <ruansy.fnst@fujitsu.com>
> ---
> hw/mem/cxl_type3.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 52647b4ac7..d8fb63b1de 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1285,6 +1285,9 @@ static const QemuUUID memory_module_uuid = {
> 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74),
> };
>
> +#define CXL_GMER_DPA_VOLATILE BIT(0)
> +#define CXL_GMER_DPA_NOT_REPAIRABLE BIT(1)
> +
> #define CXL_GMER_VALID_CHANNEL BIT(0)
> #define CXL_GMER_VALID_RANK BIT(1)
> #define CXL_GMER_VALID_DEVICE BIT(2)
> @@ -1348,6 +1351,9 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
> cxl_device_get_timestamp(&ct3d->cxl_dstate));
>
> + if (ct3d->hostvmem) {
> + dpa |= CXL_GMER_DPA_VOLATILE;
> + }
The presence of volatile memory isn't sufficient. You may have a device
with both volatile and persistent memory. It will get even fiddlier with
Dynamic Capacity which will need checking as well once that support is
ready.
> stq_le_p(&gem.phys_addr, dpa);
> gem.descriptor = descriptor;
> gem.type = type;
next prev parent reply other threads:[~2024-02-13 16:28 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-09 11:54 [RFC PATCH SET] cxl: add poison event handler Shiyang Ruan via
2024-02-09 11:54 ` [RFC PATCH 1/2] hw/cxl/type3: add missing flag bit for GMER Shiyang Ruan via
2024-02-13 16:27 ` Jonathan Cameron via [this message]
2024-02-09 11:54 ` [RFC PATCH 2/2] hw/cxl/type3: send a GMER while injecting poison Shiyang Ruan via
2024-02-13 16:32 ` Jonathan Cameron via
2024-02-09 11:54 ` [RFC PATCH 1/5] cxl/core: correct length of DPA field masks Shiyang Ruan via
2024-02-10 6:34 ` Dan Williams
2024-02-19 10:49 ` Shiyang Ruan via
2024-02-22 2:27 ` Dan Williams
2024-02-09 11:54 ` [RFC PATCH 2/5] cxl/core: introduce cxl_memdev_dpa_to_hpa() Shiyang Ruan via
2024-02-10 6:39 ` Dan Williams
2024-02-09 11:54 ` [RFC PATCH 3/5] cxl/core: introduce cxl_mem_report_poison() Shiyang Ruan via
2024-02-10 6:46 ` Dan Williams
2024-03-14 15:23 ` Shiyang Ruan via
2024-02-15 1:19 ` Tony Luck
2024-02-09 11:54 ` [RFC PATCH 4/5] cxl/core: add report option for cxl_mem_get_poison() Shiyang Ruan via
2024-02-10 6:49 ` Dan Williams
2024-03-14 15:01 ` Shiyang Ruan via
2024-02-09 11:54 ` [RFC PATCH 5/5] cxl/core: add poison injection event handler Shiyang Ruan via
2024-02-10 6:54 ` Dan Williams
2024-02-13 16:51 ` Jonathan Cameron via
2024-03-15 2:29 ` Shiyang Ruan via
2024-04-05 17:35 ` Jonathan Cameron via
2024-02-13 0:20 ` [RFC PATCH SET] cxl: add poison " Dave Jiang
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