[PATCH 0/2] RISC-V: Add Ztso extension

[PATCH 0/2] RISC-V: Add Ztso extension

[Christoph Müllner]

The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
which can be found here:
  https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
This patch did not apply cleanly but the necessary changes were trivial.
There was a request to extend the commit message, which is part of the
posted patch of this series.  As this patch was reviewed a year ago,
I believe it could be merged.

The second patch simply exposes Ztso via hwprobe.

Relevant in this context might be also, that Richard's patch to improve
TCG's memory barrier selection depending on host and guest memory ordering
landed in June 2023:
  https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/

The first patch was already sent as part of an RFC series for Ssdtso:
  https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
Since I don't want to keep this patch until the ratification of Ssdtso,
I would like to get this merged independent of Ssdtso.

This series is based on today's riscv-to-apply.next with my other series
that adds the new hwprobe keys
(https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).

This series can also be found here:
  https://github.com/cmuellner/qemu/tree/ztso

Christoph Müllner (1):
  linux-user/riscv: Add Ztso extension to hwprobe

Palmer Dabbelt (1):
  RISC-V: Add support for Ztso

 linux-user/syscall.c                    |  3 +++
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
 target/riscv/translate.c                |  3 +++
 7 files changed, 51 insertions(+), 5 deletions(-)

-- 
2.43.0

[PATCH 1/2] RISC-V: Add support for Ztso

[Christoph Müllner]

From: Palmer Dabbelt <palmer@rivosinc.com>

The Ztso extension is already ratified, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker hosts.  We need no fences for AMOs as
they're already SC, the places we need barriers are described.
These fences are placed in the RISC-V backend rather than TCG as is
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
likely soon dynamic) hart memory models.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
 target/riscv/translate.c                |  3 +++
 6 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b8d001d23..b679ecd8c7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -143,6 +143,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
+    ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
@@ -1488,6 +1489,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
     MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
     MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
+    MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
 
     MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
     MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 833bf58217..afba8ed0b2 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -71,6 +71,7 @@ struct RISCVCPUConfig {
     bool ext_zihintntl;
     bool ext_zihintpause;
     bool ext_zihpm;
+    bool ext_ztso;
     bool ext_smstateen;
     bool ext_sstc;
     bool ext_svadu;
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 267930e5bc..4a9e4591d1 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -40,7 +40,11 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
     tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
-    if (a->aq) {
+    /*
+     * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
+     * AMOs.  Instead treat them like loads.
+     */
+    if (a->aq || ctx->ztso) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
 
@@ -76,9 +80,10 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     gen_set_label(l1);
     /*
      * Address comparison failure.  However, we still need to
-     * provide the memory barrier implied by AQ/RL.
+     * provide the memory barrier implied by AQ/RL/TSO.
      */
-    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+    TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
+    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
     gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
 
     gen_set_label(l2);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index faf6d65064..ad40d3e87f 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -266,12 +266,20 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
 
 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
+    bool out;
+
     decode_save_opc(ctx);
     if (get_xl(ctx) == MXL_RV128) {
-        return gen_load_i128(ctx, a, memop);
+        out = gen_load_i128(ctx, a, memop);
     } else {
-        return gen_load_tl(ctx, a, memop);
+        out = gen_load_tl(ctx, a, memop);
+    }
+
+    if (ctx->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
+
+    return out;
 }
 
 static bool trans_lb(DisasContext *ctx, arg_lb *a)
@@ -328,6 +336,10 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
     TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
+    if (ctx->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+    }
+
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab434..742008f58b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -636,8 +636,28 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
 
+    /*
+     * According to the specification
+     *
+     *   Additionally, if the Ztso extension is implemented, then vector memory
+     *   instructions in the V extension and Zve family of extensions follow
+     *   RVTSO at the instruction level.  The Ztso extension does not
+     *   strengthen the ordering of intra-instruction element accesses.
+     *
+     * as a result neither ordered nor unordered accesses from the V
+     * instructions need ordering within the loop but we do still need barriers
+     * around the loop.
+     */
+    if (is_store && s->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+    }
+
     fn(dest, mask, base, tcg_env, desc);
 
+    if (!is_store && s->ztso) {
+        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+    }
+
     if (!is_store) {
         mark_vs_dirty(s);
     }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b2b9..ea5d52b2ef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -109,6 +109,8 @@ typedef struct DisasContext {
     /* PointerMasking extension */
     bool pm_mask_enabled;
     bool pm_base_enabled;
+    /* Ztso */
+    bool ztso;
     /* Use icount trigger for native debug */
     bool itrigger;
     /* FRM is known to contain a valid value. */
@@ -1196,6 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->cs = cs;
     ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
+    ctx->ztso = cpu->cfg.ext_ztso;
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
-- 
2.43.0

Re: [PATCH 1/2] RISC-V: Add support for Ztso

[Alistair Francis]

On Wed, Feb 7, 2024 at 10:25 PM Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> The Ztso extension is already ratified, this adds it as a CPU property
> and adds various fences throughout the port in order to allow TSO
> targets to function on weaker hosts.  We need no fences for AMOs as
> they're already SC, the places we need barriers are described.
> These fences are placed in the RISC-V backend rather than TCG as is
> planned for x86-on-arm64 because RISC-V allows heterogeneous (and
> likely soon dynamic) hart memory models.
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                      |  2 ++
>  target/riscv/cpu_cfg.h                  |  1 +
>  target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
>  target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
>  target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
>  target/riscv/translate.c                |  3 +++
>  6 files changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1b8d001d23..b679ecd8c7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -143,6 +143,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
>      ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
>      ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
> +    ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
>      ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
>      ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
>      ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
> @@ -1488,6 +1489,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
>      MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
>      MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
> +    MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
>
>      MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
>      MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 833bf58217..afba8ed0b2 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -71,6 +71,7 @@ struct RISCVCPUConfig {
>      bool ext_zihintntl;
>      bool ext_zihintpause;
>      bool ext_zihpm;
> +    bool ext_ztso;
>      bool ext_smstateen;
>      bool ext_sstc;
>      bool ext_svadu;
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
> index 267930e5bc..4a9e4591d1 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -40,7 +40,11 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
>          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
>      }
>      tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
> -    if (a->aq) {
> +    /*
> +     * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
> +     * AMOs.  Instead treat them like loads.
> +     */
> +    if (a->aq || ctx->ztso) {
>          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
>      }
>
> @@ -76,9 +80,10 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
>      gen_set_label(l1);
>      /*
>       * Address comparison failure.  However, we still need to
> -     * provide the memory barrier implied by AQ/RL.
> +     * provide the memory barrier implied by AQ/RL/TSO.
>       */
> -    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
> +    TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
> +    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
>      gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
>
>      gen_set_label(l2);
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index faf6d65064..ad40d3e87f 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -266,12 +266,20 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
>
>  static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
>  {
> +    bool out;
> +
>      decode_save_opc(ctx);
>      if (get_xl(ctx) == MXL_RV128) {
> -        return gen_load_i128(ctx, a, memop);
> +        out = gen_load_i128(ctx, a, memop);
>      } else {
> -        return gen_load_tl(ctx, a, memop);
> +        out = gen_load_tl(ctx, a, memop);
> +    }
> +
> +    if (ctx->ztso) {
> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
>      }
> +
> +    return out;
>  }
>
>  static bool trans_lb(DisasContext *ctx, arg_lb *a)
> @@ -328,6 +336,10 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
>      TCGv addr = get_address(ctx, a->rs1, a->imm);
>      TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
>
> +    if (ctx->ztso) {
> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> +    }
> +
>      tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
>      return true;
>  }
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9e101ab434..742008f58b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -636,8 +636,28 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>      tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
>      tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
>
> +    /*
> +     * According to the specification
> +     *
> +     *   Additionally, if the Ztso extension is implemented, then vector memory
> +     *   instructions in the V extension and Zve family of extensions follow
> +     *   RVTSO at the instruction level.  The Ztso extension does not
> +     *   strengthen the ordering of intra-instruction element accesses.
> +     *
> +     * as a result neither ordered nor unordered accesses from the V
> +     * instructions need ordering within the loop but we do still need barriers
> +     * around the loop.
> +     */
> +    if (is_store && s->ztso) {
> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> +    }
> +
>      fn(dest, mask, base, tcg_env, desc);
>
> +    if (!is_store && s->ztso) {
> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
> +    }
> +
>      if (!is_store) {
>          mark_vs_dirty(s);
>      }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 177418b2b9..ea5d52b2ef 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -109,6 +109,8 @@ typedef struct DisasContext {
>      /* PointerMasking extension */
>      bool pm_mask_enabled;
>      bool pm_base_enabled;
> +    /* Ztso */
> +    bool ztso;
>      /* Use icount trigger for native debug */
>      bool itrigger;
>      /* FRM is known to contain a valid value. */
> @@ -1196,6 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->cs = cs;
>      ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
>      ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
> +    ctx->ztso = cpu->cfg.ext_ztso;
>      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
>      ctx->zero = tcg_constant_tl(0);
>      ctx->virt_inst_excp = false;
> --
> 2.43.0
>
>

[PATCH 2/2] linux-user/riscv: Add Ztso extension to hwprobe

[Christoph Müllner]

This patch exposes Ztso via hwprobe in QEMU's user space emulator.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 linux-user/syscall.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 3ba20f99ad..24fa11d946 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8826,6 +8826,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
 #define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
 #define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)
 #define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)
+#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
 #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
 #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
 
@@ -8940,6 +8941,8 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
                      RISCV_HWPROBE_EXT_ZVFHMIN : 0;
             value |= cfg->ext_zfa ?
                      RISCV_HWPROBE_EXT_ZFA : 0;
+            value |= cfg->ext_ztso ?
+                     RISCV_HWPROBE_EXT_ZTSO : 0;
             value |= cfg->ext_zacas ?
                      RISCV_HWPROBE_EXT_ZACAS : 0;
             value |= cfg->ext_zicond ?
-- 
2.43.0

Re: [PATCH 2/2] linux-user/riscv: Add Ztso extension to hwprobe

[Daniel Henrique Barboza]

On 2/7/24 09:22, Christoph Müllner wrote:
> This patch exposes Ztso via hwprobe in QEMU's user space emulator.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   linux-user/syscall.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 3ba20f99ad..24fa11d946 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8826,6 +8826,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
>   #define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
>   #define		RISCV_HWPROBE_EXT_ZVFHMIN	(1 << 31)
>   #define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)
> +#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
>   #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
>   #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
>   
> @@ -8940,6 +8941,8 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
>                        RISCV_HWPROBE_EXT_ZVFHMIN : 0;
>               value |= cfg->ext_zfa ?
>                        RISCV_HWPROBE_EXT_ZFA : 0;
> +            value |= cfg->ext_ztso ?
> +                     RISCV_HWPROBE_EXT_ZTSO : 0;
>               value |= cfg->ext_zacas ?
>                        RISCV_HWPROBE_EXT_ZACAS : 0;
>               value |= cfg->ext_zicond ?

Re: [PATCH 2/2] linux-user/riscv: Add Ztso extension to hwprobe

[Alistair Francis]

On Wed, Feb 7, 2024 at 10:25 PM Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> This patch exposes Ztso via hwprobe in QEMU's user space emulator.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  linux-user/syscall.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 3ba20f99ad..24fa11d946 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -8826,6 +8826,7 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
>  #define                RISCV_HWPROBE_EXT_ZVFH          (1 << 30)
>  #define                RISCV_HWPROBE_EXT_ZVFHMIN       (1 << 31)
>  #define                RISCV_HWPROBE_EXT_ZFA           (1ULL << 32)
> +#define                RISCV_HWPROBE_EXT_ZTSO          (1ULL << 33)
>  #define                RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
>  #define                RISCV_HWPROBE_EXT_ZICOND        (1ULL << 35)
>
> @@ -8940,6 +8941,8 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
>                       RISCV_HWPROBE_EXT_ZVFHMIN : 0;
>              value |= cfg->ext_zfa ?
>                       RISCV_HWPROBE_EXT_ZFA : 0;
> +            value |= cfg->ext_ztso ?
> +                     RISCV_HWPROBE_EXT_ZTSO : 0;
>              value |= cfg->ext_zacas ?
>                       RISCV_HWPROBE_EXT_ZACAS : 0;
>              value |= cfg->ext_zicond ?
> --
> 2.43.0
>
>

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Daniel Henrique Barboza]

On 2/7/24 09:22, Christoph Müllner wrote:
> The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
> which can be found here:
>    https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
> This patch did not apply cleanly but the necessary changes were trivial.
> There was a request to extend the commit message, which is part of the
> posted patch of this series.  As this patch was reviewed a year ago,
> I believe it could be merged.
> 
> The second patch simply exposes Ztso via hwprobe.

It's also worth mentioning that the second patch relies on:

"[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"

To be applied beforehand.



Thanks,

Daniel


> 
> Relevant in this context might be also, that Richard's patch to improve
> TCG's memory barrier selection depending on host and guest memory ordering
> landed in June 2023:
>    https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
> 
> The first patch was already sent as part of an RFC series for Ssdtso:
>    https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
> Since I don't want to keep this patch until the ratification of Ssdtso,
> I would like to get this merged independent of Ssdtso.
> 
> This series is based on today's riscv-to-apply.next with my other series
> that adds the new hwprobe keys
> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> 
> This series can also be found here:
>    https://github.com/cmuellner/qemu/tree/ztso
> 
> Christoph Müllner (1):
>    linux-user/riscv: Add Ztso extension to hwprobe
> 
> Palmer Dabbelt (1):
>    RISC-V: Add support for Ztso
> 
>   linux-user/syscall.c                    |  3 +++
>   target/riscv/cpu.c                      |  2 ++
>   target/riscv/cpu_cfg.h                  |  1 +
>   target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
>   target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
>   target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
>   target/riscv/translate.c                |  3 +++
>   7 files changed, 51 insertions(+), 5 deletions(-)
> 

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Christoph Müllner]

On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 2/7/24 09:22, Christoph Müllner wrote:
> > The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
> > which can be found here:
> >    https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
> > This patch did not apply cleanly but the necessary changes were trivial.
> > There was a request to extend the commit message, which is part of the
> > posted patch of this series.  As this patch was reviewed a year ago,
> > I believe it could be merged.
> >
> > The second patch simply exposes Ztso via hwprobe.
>
> It's also worth mentioning that the second patch relies on:
>
> "[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"
>
> To be applied beforehand.

Indeed! Therefore, the end of the cover letter contains the following paragraph:
"""
This series is based on today's riscv-to-apply.next with my other series
that adds the new hwprobe keys
(https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
"""

To ease reviewing and testing for others, I've also created a remote
branch on GitHub.

Thanks for reviewing!

>
>
>
> Thanks,
>
> Daniel
>
>
> >
> > Relevant in this context might be also, that Richard's patch to improve
> > TCG's memory barrier selection depending on host and guest memory ordering
> > landed in June 2023:
> >    https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
> >
> > The first patch was already sent as part of an RFC series for Ssdtso:
> >    https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
> > Since I don't want to keep this patch until the ratification of Ssdtso,
> > I would like to get this merged independent of Ssdtso.
> >
> > This series is based on today's riscv-to-apply.next with my other series
> > that adds the new hwprobe keys
> > (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> >
> > This series can also be found here:
> >    https://github.com/cmuellner/qemu/tree/ztso
> >
> > Christoph Müllner (1):
> >    linux-user/riscv: Add Ztso extension to hwprobe
> >
> > Palmer Dabbelt (1):
> >    RISC-V: Add support for Ztso
> >
> >   linux-user/syscall.c                    |  3 +++
> >   target/riscv/cpu.c                      |  2 ++
> >   target/riscv/cpu_cfg.h                  |  1 +
> >   target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
> >   target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
> >   target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
> >   target/riscv/translate.c                |  3 +++
> >   7 files changed, 51 insertions(+), 5 deletions(-)
> >

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Daniel Henrique Barboza]

On 2/14/24 10:38, Christoph Müllner wrote:
> On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>>
>>
>> On 2/7/24 09:22, Christoph Müllner wrote:
>>> The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
>>> which can be found here:
>>>     https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
>>> This patch did not apply cleanly but the necessary changes were trivial.
>>> There was a request to extend the commit message, which is part of the
>>> posted patch of this series.  As this patch was reviewed a year ago,
>>> I believe it could be merged.
>>>
>>> The second patch simply exposes Ztso via hwprobe.
>>
>> It's also worth mentioning that the second patch relies on:
>>
>> "[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"
>>
>> To be applied beforehand.
> 
> Indeed! Therefore, the end of the cover letter contains the following paragraph:
> """
> This series is based on today's riscv-to-apply.next with my other series
> that adds the new hwprobe keys
> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> """

I guess it's also worth mentioning that I didn't pay enough attention to the
cover letter :skull:



Thanks,

Daniel

> 
> To ease reviewing and testing for others, I've also created a remote
> branch on GitHub.
> 
> Thanks for reviewing!
> 
>>
>>
>>
>> Thanks,
>>
>> Daniel
>>
>>
>>>
>>> Relevant in this context might be also, that Richard's patch to improve
>>> TCG's memory barrier selection depending on host and guest memory ordering
>>> landed in June 2023:
>>>     https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
>>>
>>> The first patch was already sent as part of an RFC series for Ssdtso:
>>>     https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
>>> Since I don't want to keep this patch until the ratification of Ssdtso,
>>> I would like to get this merged independent of Ssdtso.
>>>
>>> This series is based on today's riscv-to-apply.next with my other series
>>> that adds the new hwprobe keys
>>> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
>>>
>>> This series can also be found here:
>>>     https://github.com/cmuellner/qemu/tree/ztso
>>>
>>> Christoph Müllner (1):
>>>     linux-user/riscv: Add Ztso extension to hwprobe
>>>
>>> Palmer Dabbelt (1):
>>>     RISC-V: Add support for Ztso
>>>
>>>    linux-user/syscall.c                    |  3 +++
>>>    target/riscv/cpu.c                      |  2 ++
>>>    target/riscv/cpu_cfg.h                  |  1 +
>>>    target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
>>>    target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
>>>    target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
>>>    target/riscv/translate.c                |  3 +++
>>>    7 files changed, 51 insertions(+), 5 deletions(-)
>>>

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Andrew Jones]

On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
> On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
> >
> >
> >
> > On 2/7/24 09:22, Christoph Müllner wrote:
> > > The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
> > > which can be found here:
> > >    https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
> > > This patch did not apply cleanly but the necessary changes were trivial.
> > > There was a request to extend the commit message, which is part of the
> > > posted patch of this series.  As this patch was reviewed a year ago,
> > > I believe it could be merged.
> > >
> > > The second patch simply exposes Ztso via hwprobe.
> >
> > It's also worth mentioning that the second patch relies on:
> >
> > "[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"
> >
> > To be applied beforehand.
> 
> Indeed! Therefore, the end of the cover letter contains the following paragraph:
> """
> This series is based on today's riscv-to-apply.next with my other series
> that adds the new hwprobe keys
> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> """

I think a line like

Based-on: 20240207115926.887816-1-christoph.muellner@vrull.eu

in the cover letter would allow the automated tools to green-light this
series too.

Thanks,
drew


> 
> To ease reviewing and testing for others, I've also created a remote
> branch on GitHub.
> 
> Thanks for reviewing!
> 
> >
> >
> >
> > Thanks,
> >
> > Daniel
> >
> >
> > >
> > > Relevant in this context might be also, that Richard's patch to improve
> > > TCG's memory barrier selection depending on host and guest memory ordering
> > > landed in June 2023:
> > >    https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
> > >
> > > The first patch was already sent as part of an RFC series for Ssdtso:
> > >    https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
> > > Since I don't want to keep this patch until the ratification of Ssdtso,
> > > I would like to get this merged independent of Ssdtso.
> > >
> > > This series is based on today's riscv-to-apply.next with my other series
> > > that adds the new hwprobe keys
> > > (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> > >
> > > This series can also be found here:
> > >    https://github.com/cmuellner/qemu/tree/ztso
> > >
> > > Christoph Müllner (1):
> > >    linux-user/riscv: Add Ztso extension to hwprobe
> > >
> > > Palmer Dabbelt (1):
> > >    RISC-V: Add support for Ztso
> > >
> > >   linux-user/syscall.c                    |  3 +++
> > >   target/riscv/cpu.c                      |  2 ++
> > >   target/riscv/cpu_cfg.h                  |  1 +
> > >   target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
> > >   target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
> > >   target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
> > >   target/riscv/translate.c                |  3 +++
> > >   7 files changed, 51 insertions(+), 5 deletions(-)
> > >

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Christoph Müllner]

On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
> > On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> > <dbarboza@ventanamicro.com> wrote:
> > >
> > >
> > >
> > > On 2/7/24 09:22, Christoph Müllner wrote:
> > > > The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
> > > > which can be found here:
> > > >    https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
> > > > This patch did not apply cleanly but the necessary changes were trivial.
> > > > There was a request to extend the commit message, which is part of the
> > > > posted patch of this series.  As this patch was reviewed a year ago,
> > > > I believe it could be merged.
> > > >
> > > > The second patch simply exposes Ztso via hwprobe.
> > >
> > > It's also worth mentioning that the second patch relies on:
> > >
> > > "[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"
> > >
> > > To be applied beforehand.
> >
> > Indeed! Therefore, the end of the cover letter contains the following paragraph:
> > """
> > This series is based on today's riscv-to-apply.next with my other series
> > that adds the new hwprobe keys
> > (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> > """
>
> I think a line like
>
> Based-on: 20240207115926.887816-1-christoph.muellner@vrull.eu
>
> in the cover letter would allow the automated tools to green-light this
> series too.

Should I resend?

>
> Thanks,
> drew
>
>
> >
> > To ease reviewing and testing for others, I've also created a remote
> > branch on GitHub.
> >
> > Thanks for reviewing!
> >
> > >
> > >
> > >
> > > Thanks,
> > >
> > > Daniel
> > >
> > >
> > > >
> > > > Relevant in this context might be also, that Richard's patch to improve
> > > > TCG's memory barrier selection depending on host and guest memory ordering
> > > > landed in June 2023:
> > > >    https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
> > > >
> > > > The first patch was already sent as part of an RFC series for Ssdtso:
> > > >    https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
> > > > Since I don't want to keep this patch until the ratification of Ssdtso,
> > > > I would like to get this merged independent of Ssdtso.
> > > >
> > > > This series is based on today's riscv-to-apply.next with my other series
> > > > that adds the new hwprobe keys
> > > > (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
> > > >
> > > > This series can also be found here:
> > > >    https://github.com/cmuellner/qemu/tree/ztso
> > > >
> > > > Christoph Müllner (1):
> > > >    linux-user/riscv: Add Ztso extension to hwprobe
> > > >
> > > > Palmer Dabbelt (1):
> > > >    RISC-V: Add support for Ztso
> > > >
> > > >   linux-user/syscall.c                    |  3 +++
> > > >   target/riscv/cpu.c                      |  2 ++
> > > >   target/riscv/cpu_cfg.h                  |  1 +
> > > >   target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
> > > >   target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
> > > >   target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
> > > >   target/riscv/translate.c                |  3 +++
> > > >   7 files changed, 51 insertions(+), 5 deletions(-)
> > > >

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Daniel Henrique Barboza]

On 2/15/24 06:53, Christoph Müllner wrote:
> On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>>
>> On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
>>> On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
>>> <dbarboza@ventanamicro.com> wrote:
>>>>
>>>>
>>>>
>>>> On 2/7/24 09:22, Christoph Müllner wrote:
>>>>> The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
>>>>> which can be found here:
>>>>>     https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
>>>>> This patch did not apply cleanly but the necessary changes were trivial.
>>>>> There was a request to extend the commit message, which is part of the
>>>>> posted patch of this series.  As this patch was reviewed a year ago,
>>>>> I believe it could be merged.
>>>>>
>>>>> The second patch simply exposes Ztso via hwprobe.
>>>>
>>>> It's also worth mentioning that the second patch relies on:
>>>>
>>>> "[PATCH 0/2] linux-user/riscv: Sync hwprobe keys with kernel"
>>>>
>>>> To be applied beforehand.
>>>
>>> Indeed! Therefore, the end of the cover letter contains the following paragraph:
>>> """
>>> This series is based on today's riscv-to-apply.next with my other series
>>> that adds the new hwprobe keys
>>> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
>>> """
>>
>> I think a line like
>>
>> Based-on: 20240207115926.887816-1-christoph.muellner@vrull.eu
>>
>> in the cover letter would allow the automated tools to green-light this
>> series too.
> 
> Should I resend?

You can add the "Based-on" line as Drew said in case a second version is needed.
Don't worry about it.


Thanks,

Daniel

> 
>>
>> Thanks,
>> drew
>>
>>
>>>
>>> To ease reviewing and testing for others, I've also created a remote
>>> branch on GitHub.
>>>
>>> Thanks for reviewing!
>>>
>>>>
>>>>
>>>>
>>>> Thanks,
>>>>
>>>> Daniel
>>>>
>>>>
>>>>>
>>>>> Relevant in this context might be also, that Richard's patch to improve
>>>>> TCG's memory barrier selection depending on host and guest memory ordering
>>>>> landed in June 2023:
>>>>>     https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
>>>>>
>>>>> The first patch was already sent as part of an RFC series for Ssdtso:
>>>>>     https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
>>>>> Since I don't want to keep this patch until the ratification of Ssdtso,
>>>>> I would like to get this merged independent of Ssdtso.
>>>>>
>>>>> This series is based on today's riscv-to-apply.next with my other series
>>>>> that adds the new hwprobe keys
>>>>> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
>>>>>
>>>>> This series can also be found here:
>>>>>     https://github.com/cmuellner/qemu/tree/ztso
>>>>>
>>>>> Christoph Müllner (1):
>>>>>     linux-user/riscv: Add Ztso extension to hwprobe
>>>>>
>>>>> Palmer Dabbelt (1):
>>>>>     RISC-V: Add support for Ztso
>>>>>
>>>>>    linux-user/syscall.c                    |  3 +++
>>>>>    target/riscv/cpu.c                      |  2 ++
>>>>>    target/riscv/cpu_cfg.h                  |  1 +
>>>>>    target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
>>>>>    target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
>>>>>    target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
>>>>>    target/riscv/translate.c                |  3 +++
>>>>>    7 files changed, 51 insertions(+), 5 deletions(-)
>>>>>

Re: [PATCH 0/2] RISC-V: Add Ztso extension

[Alistair Francis]

On Wed, Feb 7, 2024 at 10:24 PM Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
> which can be found here:
>   https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
> This patch did not apply cleanly but the necessary changes were trivial.
> There was a request to extend the commit message, which is part of the
> posted patch of this series.  As this patch was reviewed a year ago,
> I believe it could be merged.
>
> The second patch simply exposes Ztso via hwprobe.
>
> Relevant in this context might be also, that Richard's patch to improve
> TCG's memory barrier selection depending on host and guest memory ordering
> landed in June 2023:
>   https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/
>
> The first patch was already sent as part of an RFC series for Ssdtso:
>   https://lists.nongnu.org/archive/html/qemu-devel/2023-11/msg02962.html
> Since I don't want to keep this patch until the ratification of Ssdtso,
> I would like to get this merged independent of Ssdtso.
>
> This series is based on today's riscv-to-apply.next with my other series
> that adds the new hwprobe keys
> (https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg01293.html).
>
> This series can also be found here:
>   https://github.com/cmuellner/qemu/tree/ztso
>
> Christoph Müllner (1):
>   linux-user/riscv: Add Ztso extension to hwprobe
>
> Palmer Dabbelt (1):
>   RISC-V: Add support for Ztso

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  linux-user/syscall.c                    |  3 +++
>  target/riscv/cpu.c                      |  2 ++
>  target/riscv/cpu_cfg.h                  |  1 +
>  target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
>  target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
>  target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
>  target/riscv/translate.c                |  3 +++
>  7 files changed, 51 insertions(+), 5 deletions(-)
>
> --
> 2.43.0
>
>