From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor@kernel.org>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH v3 3/6] target/riscv: add remaining named features
Date: Thu, 15 Feb 2024 15:26:18 +0100 [thread overview]
Message-ID: <20240215-55440212b4d6cde9feab5d94@orel> (raw)
In-Reply-To: <20240215-alkaline-saturday-275cd8e3aa39@spud>
On Thu, Feb 15, 2024 at 01:33:47PM +0000, Conor Dooley wrote:
> On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
> > The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> > until now, we were implying that they were available.
> >
> > We can't do this anymore since named features also has a riscv,isa
> > entry. Let's add them to riscv_cpu_named_features[].
> >
> > Instead of adding one bool for each named feature that we'll always
> > implement, i.e. can't be turned off, add a 'ext_always_enabled' bool in
> > cpu->cfg. This bool will be set to 'true' in TCG accel init, and all
> > named features will point to it. This also means that KVM won't see
> > these features as always enable, which is our intention.
> >
> > If any accelerator adds support to disable one of these features, we'll
> > have to promote them to regular extensions and allow users to disable it
> > via command line.
> >
> > After this patch, here's the riscv,isa from a buildroot using the
> > 'rva22s64' CPU:
>
> Why does an "rva22s64" cpu have "zicclsm" in it? Isn't zicclsm only
> present in "u" profiles?
"s" profiles mandate all the "u" profile mandatory extensions. For example
6.2.2 says
"""
The RVA22S64 mandatory unprivileged extensions include all the mandatory unprivileged
extensions in RVA22U64.
"""
>
> > # cat /proc/device-tree/cpus/cpu@0/riscv,isa
> > rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
> > zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
> > zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
>
> I want to raise my frustration with the crock we've been given here by
> RVI. Any "named feature" that just creates a name for something that
> already is assumed is completely useless, and DT property that is used
> to communicate it's presence cannot be used - instead the property needs
> to be inverted - indicating the absence of that named feature.
>
> Without the inversion, software that parses "riscv,isa" cannot make any
> determination based on the absence of the property - it could be parsing
> an old DT that does not have the property or it could be parsing the DT
> of a system that does not support the extension.
I'm guessing any platform which wants to advertise that it's compliant
with a profile will update its hardware descriptions to ensure all the
profile's mandatory extensions are presented. But, I think I understand
your concern. If somebody is parsing the ISA string as way to determine
if the platform is compliant with a profile, then they may get a false
negative due to the ISA string missing a newly named feature. I'm not
sure how much of a problem that will be in practice, though, since testing
for profile compliance, just for the sake of it, doesn't seem very useful.
Software really only needs to know which extensions are available and if
it's an old feature that got newly named, then software likely already
has another way of detecting it.
>
> This is part of why I deprecated `riscv,isa`. It's the same problem as
> with "zifencei" et al - does a system with `riscv,isa = "rv64imac"`
> support fence.i?
Yes, there's a handful of these messy things and the first profiles
expose them since they're trying to define them. Fingers crossed that
the next profiles won't have to name old features. FWIW, I at least
don't see any "This is a new extension name for this feature" notes in
the RVA23 profile.
Thanks,
drew
next prev parent reply other threads:[~2024-02-15 14:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 15:21 [PATCH v3 0/6] riscv: named features riscv,isa, 'svade' rework Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 2/6] target/riscv: add riscv,isa to named features Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 3/6] target/riscv: add remaining " Daniel Henrique Barboza
2024-02-05 14:04 ` Andrew Jones
2024-02-15 4:20 ` Alistair Francis
2024-02-15 13:33 ` Conor Dooley
2024-02-15 14:13 ` Daniel Henrique Barboza
2024-02-15 14:39 ` Andrew Jones
2024-02-15 14:26 ` Andrew Jones [this message]
2024-02-15 16:34 ` Conor Dooley
2024-02-15 19:11 ` Andrew Jones
2024-02-15 19:59 ` Conor Dooley
2024-02-16 0:12 ` Alistair Francis
2024-02-16 15:08 ` Conor Dooley
2024-02-02 15:21 ` [PATCH v3 4/6] target/riscv: Reset henvcfg to zero Daniel Henrique Barboza
2024-02-15 5:38 ` Alistair Francis
2024-02-02 15:21 ` [PATCH v3 5/6] target/riscv: Gate hardware A/D PTE bit updating Daniel Henrique Barboza
2024-02-15 5:46 ` Alistair Francis
2024-02-02 15:21 ` [PATCH v3 6/6] target/riscv: Promote svade to a normal extension Daniel Henrique Barboza
2024-02-15 5:41 ` Alistair Francis
2024-02-15 9:52 ` [PATCH v3 0/6] riscv: named features riscv,isa, 'svade' rework Alistair Francis
2024-02-15 21:28 ` Daniel Henrique Barboza
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