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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
	"Gregory Price" <gregory.price@memverge.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Sajjan Rao" <sajjanr@gmail.com>,
	"Dimitrios Palyvos" <dimitrios.palyvos@zptcorp.com>,
	richard.henderson@linaro.org,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	linux-cxl@vger.kernel.org
Subject: Re: [PATCH 2/3] target/i386: Enable page walking from MMIO memory
Date: Thu, 15 Feb 2024 15:56:04 +0000	[thread overview]
Message-ID: <20240215155604.000078b0@Huawei.com> (raw)
In-Reply-To: <5b53790b-8f94-4b21-b1da-e7f278af0dd7@linaro.org>

On Thu, 15 Feb 2024 16:31:26 +0100
Philippe Mathieu-Daudé <philmd@linaro.org> wrote:

> On 15/2/24 16:01, Jonathan Cameron via wrote:
> > From: Gregory Price <gregory.price@memverge.com>
> > 
> > CXL emulation of interleave requires read and write hooks due to
> > requirement for subpage granularity. The Linux kernel stack now enables
> > using this memory as conventional memory in a separate NUMA node. If a
> > process is deliberately forced to run from that node
> > $ numactl --membind=1 ls
> > the page table walk on i386 fails.
> > 
> > Useful part of backtrace:
> > 
> >      (cpu=cpu@entry=0x555556fd9000, fmt=fmt@entry=0x555555fe3378 "cpu_io_recompile: could not find TB for pc=%p")
> >      at ../../cpu-target.c:359
> >      (retaddr=0, addr=19595792376, attrs=..., xlat=<optimized out>, cpu=0x555556fd9000, out_offset=<synthetic pointer>)
> >      at ../../accel/tcg/cputlb.c:1339
> >      (cpu=0x555556fd9000, full=0x7fffee0d96e0, ret_be=ret_be@entry=0, addr=19595792376, size=size@entry=8, mmu_idx=4, type=MMU_DATA_LOAD, ra=0) at ../../accel/tcg/cputlb.c:2030
> >      (cpu=cpu@entry=0x555556fd9000, p=p@entry=0x7ffff56fddc0, mmu_idx=<optimized out>, type=type@entry=MMU_DATA_LOAD, memop=<optimized out>, ra=ra@entry=0) at ../../accel/tcg/cputlb.c:2356
> >      (cpu=cpu@entry=0x555556fd9000, addr=addr@entry=19595792376, oi=oi@entry=52, ra=ra@entry=0, access_type=access_type@entry=MMU_DATA_LOAD) at ../../accel/tcg/cputlb.c:2439
> >      at ../../accel/tcg/ldst_common.c.inc:301
> >      at ../../target/i386/tcg/sysemu/excp_helper.c:173
> >      (err=0x7ffff56fdf80, out=0x7ffff56fdf70, mmu_idx=0, access_type=MMU_INST_FETCH, addr=18446744072116178925, env=0x555556fdb7c0)
> >      at ../../target/i386/tcg/sysemu/excp_helper.c:578
> >      (cs=0x555556fd9000, addr=18446744072116178925, size=<optimized out>, access_type=MMU_INST_FETCH, mmu_idx=0, probe=<optimized out>, retaddr=0) at ../../target/i386/tcg/sysemu/excp_helper.c:604
> > 
> > Avoid this by plumbing the address all the way down from
> > x86_cpu_tlb_fill() where is available as retaddr to the actual accessors
> > which provide it to probe_access_full() which already handles MMIO accesses.
> >   
> 
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Good point!  Sorry Peter.

> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Thanks
> 
> > Signed-off-by: Gregory Price <gregory.price@memverge.com>
> > 
> > ---
> > Patch posted in reply to thread:
> > https://lore.kernel.org/qemu-devel/ZbvpSaOXzZkqDd6c@memverge.com/
> > 
> > I checked Gregory was fine with me adding Sign-off / author via the CXL discord.
> > ---
> >   target/i386/tcg/sysemu/excp_helper.c | 57 +++++++++++++++-------------
> >   1 file changed, 30 insertions(+), 27 deletions(-)  
> 



  reply	other threads:[~2024-02-15 15:57 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-15 15:01 [PATCH 0/3 qemu] tcg/i386: Page tables in MMIO memory fixes (CXL) Jonathan Cameron via
2024-02-15 15:01 ` [PATCH 1/3] accel/tcg: Set can_do_io at at start of lookup_tb_ptr helper Jonathan Cameron via
2024-02-15 15:11   ` Peter Maydell
2024-02-15 16:04     ` Jonathan Cameron via
2024-02-15 19:11   ` Richard Henderson
2024-02-15 15:01 ` [PATCH 2/3] target/i386: Enable page walking from MMIO memory Jonathan Cameron via
2024-02-15 15:31   ` Philippe Mathieu-Daudé
2024-02-15 15:56     ` Jonathan Cameron via [this message]
2024-02-15 19:21   ` Richard Henderson
2024-02-15 19:31     ` Richard Henderson
2024-02-15 15:01 ` [PATCH 3/3] tcg: Avoid double lock if page tables happen to be in mmio memory Jonathan Cameron via
2024-02-15 15:33   ` Philippe Mathieu-Daudé
2024-02-15 16:11     ` Jonathan Cameron via
2024-02-15 16:11   ` Peter Maydell
2024-02-15 17:34     ` Jonathan Cameron via
2024-02-15 19:30   ` Richard Henderson
2024-02-19 12:14     ` Jonathan Cameron via
2024-02-20 11:56       ` Alex Bennée

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