From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-ppc@nongnu.org,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Subject: [PULL 12/49] target/ppc: Rename registers to match ISA
Date: Mon, 19 Feb 2024 18:29:01 +1000 [thread overview]
Message-ID: <20240219082938.238302-13-npiggin@gmail.com> (raw)
In-Reply-To: <20240219082938.238302-1-npiggin@gmail.com>
Several registers have names that don't match the ISA (or convention
with other QEMU PPC registers), making them unintuitive to use with
GDB.
Fortunately most of these registers are obscure and/or have not been
correctly implemented in the gdb server (e.g., DEC, TB, CFAR), so risk
of breaking users should be low.
QEMU should follow the ISA for register name convention (where there is
no established GDB name).
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu_init.c | 20 ++++++++++----------
target/ppc/helper_regs.c | 2 +-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 9931372a08..9bccddb350 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5062,7 +5062,7 @@ static void register_970_hid_sprs(CPUPPCState *env)
static void register_970_hior_sprs(CPUPPCState *env)
{
- spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
@@ -5070,11 +5070,11 @@ static void register_970_hior_sprs(CPUPPCState *env)
static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
- spr_register(env, SPR_CTRL, "SPR_CTRL",
+ spr_register(env, SPR_CTRL, "CTRL",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_CTRL,
0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ spr_register(env, SPR_UCTRL, "UCTRL",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -5465,7 +5465,7 @@ static void register_book3s_purr_sprs(CPUPPCState *env)
static void register_power6_dbg_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_CFAR, "SPR_CFAR",
+ spr_register(env, SPR_CFAR, "CFAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
@@ -5483,7 +5483,7 @@ static void register_power5p_common_sprs(CPUPPCState *env)
static void register_power6_common_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ spr_register_kvm(env, SPR_DSCR, "DSCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DSCR, 0x00000000);
@@ -5695,7 +5695,7 @@ static void register_power8_book4_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
/* PID is only in BookE in ISA v2.07 */
- spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pidr,
KVM_REG_PPC_PID, 0);
@@ -5716,7 +5716,7 @@ static void register_power7_book4_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
/* PID is only in BookE in ISA v2.06 */
- spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic32,
KVM_REG_PPC_PID, 0);
@@ -5750,7 +5750,7 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x0000000000000000);
/* PID is part of the BookS ISA from v3.0 */
- spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pidr,
KVM_REG_PPC_PID, 0);
@@ -5791,7 +5791,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic32,
0);
- spr_register(env, SPR_UDEXCR, "DEXCR",
+ spr_register(env, SPR_UDEXCR, "UDEXCR",
&spr_read_dexcr_ureg, SPR_NOACCESS,
&spr_read_dexcr_ureg, SPR_NOACCESS,
0);
@@ -5802,7 +5802,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic32,
0);
- spr_register(env, SPR_UHDEXCR, "HDEXCR",
+ spr_register(env, SPR_UHDEXCR, "UHDEXCR",
&spr_read_dexcr_ureg, SPR_NOACCESS,
&spr_read_dexcr_ureg, SPR_NOACCESS,
0);
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index e0b2dcd02e..8324ff22db 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -490,7 +490,7 @@ void register_non_embedded_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DAR, 0x00000000);
/* Timer */
- spr_register(env, SPR_DECR, "DECR",
+ spr_register(env, SPR_DECR, "DEC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_decr, &spr_write_decr,
0x00000000);
--
2.42.0
next prev parent reply other threads:[~2024-02-19 8:36 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 8:28 [PULL 00/49] ppc-for-9.0 queue Nicholas Piggin
2024-02-19 8:28 ` [PULL 01/49] target/ppc: Fix lxv/stxv MSR facility check Nicholas Piggin
2024-02-19 8:28 ` [PULL 02/49] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-02-19 8:28 ` [PULL 03/49] tests/avocado: mark boot_linux.py long runtime instead of flaky Nicholas Piggin
2024-02-19 8:28 ` [PULL 04/49] tests/avocado: improve flaky ppc/pnv boot_linux_console.py test Nicholas Piggin
2024-02-19 8:28 ` [PULL 05/49] tests/avocado: ppc add powernv10 boot_linux_console test Nicholas Piggin
2024-02-19 8:28 ` [PULL 06/49] tests/avocado: Add ppc pseries and powernv hash MMU tests Nicholas Piggin
2024-02-19 8:28 ` [PULL 07/49] tests/avocado: Add pseries KVM boot_linux test Nicholas Piggin
2024-02-19 8:28 ` [PULL 08/49] tests/avocado: ppc add hypervisor tests Nicholas Piggin
2024-02-19 8:28 ` [PULL 09/49] tests/avocado: Add FreeBSD distro boot tests for ppc Nicholas Piggin
2024-02-19 14:49 ` BALATON Zoltan
2024-02-20 1:16 ` Nicholas Piggin
2024-02-19 8:28 ` [PULL 10/49] tests/avocado: Use default CPU for pseries machine Nicholas Piggin
2024-02-19 8:29 ` [PULL 11/49] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-02-19 8:29 ` Nicholas Piggin [this message]
2024-02-19 8:29 ` [PULL 13/49] hw/ppc/spapr: Add missing license Nicholas Piggin
2024-02-19 8:29 ` [PULL 14/49] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep Nicholas Piggin
2024-02-19 8:29 ` [PULL 15/49] hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr Nicholas Piggin
2024-02-19 8:29 ` [PULL 16/49] hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Nicholas Piggin
2024-02-19 8:29 ` [PULL 17/49] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs Nicholas Piggin
2024-02-19 8:29 ` [PULL 18/49] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS Nicholas Piggin
2024-02-19 8:29 ` [PULL 19/49] ppc/spapr: change pseries machine default to POWER10 CPU Nicholas Piggin
2024-02-19 8:29 ` [PULL 20/49] spapr: Tag pseries-2.1 - 2.11 machines as deprecated Nicholas Piggin
2024-09-16 13:14 ` Cédric Le Goater
2024-09-17 4:37 ` Harsh Prateek Bora
2024-02-19 8:29 ` [PULL 21/49] ppc/pnv: Change powernv default to powernv10 Nicholas Piggin
2024-02-19 8:29 ` [PULL 22/49] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses Nicholas Piggin
2024-02-19 14:49 ` BALATON Zoltan
2024-02-19 14:53 ` Cédric Le Goater
2024-02-19 14:55 ` Peter Maydell
2024-02-19 15:09 ` Cédric Le Goater
2024-02-19 8:29 ` [PULL 23/49] misc/pca9552: Fix inverted input status Nicholas Piggin
2024-02-19 8:29 ` [PULL 24/49] misc/pca9552: Let external devices set pca9552 inputs Nicholas Piggin
2024-02-19 8:29 ` [PULL 25/49] ppc/pnv: New powernv10-rainier machine type Nicholas Piggin
2024-02-19 8:29 ` [PULL 26/49] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control Nicholas Piggin
2024-02-19 8:29 ` [PULL 27/49] ppc/pnv: Wire up pca9552 GPIO pins " Nicholas Piggin
2024-02-19 8:29 ` [PULL 28/49] ppc/pnv: Use resettable interface to reset child I2C buses Nicholas Piggin
2024-02-19 8:29 ` [PULL 29/49] misc: Add a pca9554 GPIO device model Nicholas Piggin
2024-02-19 8:29 ` [PULL 30/49] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier Nicholas Piggin
2024-02-19 8:29 ` [PULL 31/49] ppc/pnv: Test pnv i2c master and connected devices Nicholas Piggin
2024-02-19 8:29 ` [PULL 32/49] hw/ppc: Add pnv nest pervasive common chiplet model Nicholas Piggin
2024-02-19 8:29 ` [PULL 33/49] hw/ppc: Add N1 " Nicholas Piggin
2024-02-19 8:29 ` [PULL 34/49] hw/ppc: N1 chiplet wiring Nicholas Piggin
2024-02-19 8:29 ` [PULL 35/49] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-02-19 8:29 ` [PULL 36/49] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-02-19 8:29 ` [PULL 37/49] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-02-19 8:29 ` [PULL 38/49] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2024-02-19 8:29 ` [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model Nicholas Piggin
2024-02-19 8:29 ` [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Nicholas Piggin
2024-02-19 8:29 ` [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-02-19 8:29 ` [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-02-19 8:29 ` [PULL 43/49] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-02-19 8:29 ` [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps Nicholas Piggin
2024-02-19 8:29 ` [PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing Nicholas Piggin
2024-02-19 8:29 ` [PULL 46/49] target/ppc: 4xx don't flush TLB for a newly written software TLB entry Nicholas Piggin
2024-02-19 8:29 ` [PULL 47/49] target/ppc: 4xx optimise tlbwe_lo TLB flushing Nicholas Piggin
2024-02-19 8:29 ` [PULL 48/49] target/ppc: 440 optimise tlbwe " Nicholas Piggin
2024-02-19 8:29 ` [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing Nicholas Piggin
2024-02-19 17:06 ` [PULL 00/49] ppc-for-9.0 queue Peter Maydell
2024-02-20 1:15 ` Nicholas Piggin
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