From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-ppc@nongnu.org,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 15/49] hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr
Date: Mon, 19 Feb 2024 18:29:04 +1000 [thread overview]
Message-ID: <20240219082938.238302-16-npiggin@gmail.com> (raw)
In-Reply-To: <20240219082938.238302-1-npiggin@gmail.com>
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU
facilities to use the vhyp_mmu_ prefix rather than softmmu_.
vhyp_mmu_ is chosen because the code that manipulates the hash table
via guest software hypercalls is QEMU's implementation of the PAPR
hypervisor interface, called vhyp.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[npiggin: Pick a different name, explain it in changelog.]
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_hcall.c | 4 ++--
hw/ppc/spapr_softmmu.c | 4 ++--
include/hw/ppc/spapr.h | 9 ++++++---
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 0d7d523e6d..75c2d12978 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -124,7 +124,7 @@ static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
if (kvm_enabled()) {
return H_HARDWARE;
} else if (tcg_enabled()) {
- return softmmu_resize_hpt_prepare(cpu, spapr, shift);
+ return vhyp_mmu_resize_hpt_prepare(cpu, spapr, shift);
} else {
g_assert_not_reached();
}
@@ -194,7 +194,7 @@ static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
if (kvm_enabled()) {
return H_HARDWARE;
} else if (tcg_enabled()) {
- return softmmu_resize_hpt_commit(cpu, spapr, flags, shift);
+ return vhyp_mmu_resize_hpt_commit(cpu, spapr, flags, shift);
} else {
g_assert_not_reached();
}
diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/spapr_softmmu.c
index 2fade94029..b3dd8b3a59 100644
--- a/hw/ppc/spapr_softmmu.c
+++ b/hw/ppc/spapr_softmmu.c
@@ -378,7 +378,7 @@ static void cancel_hpt_prepare(SpaprMachineState *spapr)
free_pending_hpt(pending);
}
-target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu,
+target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong shift)
{
@@ -562,7 +562,7 @@ static int rehash_hpt(PowerPCCPU *cpu,
return H_SUCCESS;
}
-target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu,
+target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong flags,
target_ulong shift)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index e91791a1a9..5b5ba9ef77 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -634,10 +634,13 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
-target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
+target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
target_ulong shift);
-target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong flags, target_ulong shift);
+target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong flags,
+ target_ulong shift);
bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
--
2.42.0
next prev parent reply other threads:[~2024-02-19 8:35 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 8:28 [PULL 00/49] ppc-for-9.0 queue Nicholas Piggin
2024-02-19 8:28 ` [PULL 01/49] target/ppc: Fix lxv/stxv MSR facility check Nicholas Piggin
2024-02-19 8:28 ` [PULL 02/49] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-02-19 8:28 ` [PULL 03/49] tests/avocado: mark boot_linux.py long runtime instead of flaky Nicholas Piggin
2024-02-19 8:28 ` [PULL 04/49] tests/avocado: improve flaky ppc/pnv boot_linux_console.py test Nicholas Piggin
2024-02-19 8:28 ` [PULL 05/49] tests/avocado: ppc add powernv10 boot_linux_console test Nicholas Piggin
2024-02-19 8:28 ` [PULL 06/49] tests/avocado: Add ppc pseries and powernv hash MMU tests Nicholas Piggin
2024-02-19 8:28 ` [PULL 07/49] tests/avocado: Add pseries KVM boot_linux test Nicholas Piggin
2024-02-19 8:28 ` [PULL 08/49] tests/avocado: ppc add hypervisor tests Nicholas Piggin
2024-02-19 8:28 ` [PULL 09/49] tests/avocado: Add FreeBSD distro boot tests for ppc Nicholas Piggin
2024-02-19 14:49 ` BALATON Zoltan
2024-02-20 1:16 ` Nicholas Piggin
2024-02-19 8:28 ` [PULL 10/49] tests/avocado: Use default CPU for pseries machine Nicholas Piggin
2024-02-19 8:29 ` [PULL 11/49] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-02-19 8:29 ` [PULL 12/49] target/ppc: Rename registers to match ISA Nicholas Piggin
2024-02-19 8:29 ` [PULL 13/49] hw/ppc/spapr: Add missing license Nicholas Piggin
2024-02-19 8:29 ` [PULL 14/49] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep Nicholas Piggin
2024-02-19 8:29 ` Nicholas Piggin [this message]
2024-02-19 8:29 ` [PULL 16/49] hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Nicholas Piggin
2024-02-19 8:29 ` [PULL 17/49] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs Nicholas Piggin
2024-02-19 8:29 ` [PULL 18/49] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS Nicholas Piggin
2024-02-19 8:29 ` [PULL 19/49] ppc/spapr: change pseries machine default to POWER10 CPU Nicholas Piggin
2024-02-19 8:29 ` [PULL 20/49] spapr: Tag pseries-2.1 - 2.11 machines as deprecated Nicholas Piggin
2024-09-16 13:14 ` Cédric Le Goater
2024-09-17 4:37 ` Harsh Prateek Bora
2024-02-19 8:29 ` [PULL 21/49] ppc/pnv: Change powernv default to powernv10 Nicholas Piggin
2024-02-19 8:29 ` [PULL 22/49] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses Nicholas Piggin
2024-02-19 14:49 ` BALATON Zoltan
2024-02-19 14:53 ` Cédric Le Goater
2024-02-19 14:55 ` Peter Maydell
2024-02-19 15:09 ` Cédric Le Goater
2024-02-19 8:29 ` [PULL 23/49] misc/pca9552: Fix inverted input status Nicholas Piggin
2024-02-19 8:29 ` [PULL 24/49] misc/pca9552: Let external devices set pca9552 inputs Nicholas Piggin
2024-02-19 8:29 ` [PULL 25/49] ppc/pnv: New powernv10-rainier machine type Nicholas Piggin
2024-02-19 8:29 ` [PULL 26/49] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control Nicholas Piggin
2024-02-19 8:29 ` [PULL 27/49] ppc/pnv: Wire up pca9552 GPIO pins " Nicholas Piggin
2024-02-19 8:29 ` [PULL 28/49] ppc/pnv: Use resettable interface to reset child I2C buses Nicholas Piggin
2024-02-19 8:29 ` [PULL 29/49] misc: Add a pca9554 GPIO device model Nicholas Piggin
2024-02-19 8:29 ` [PULL 30/49] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier Nicholas Piggin
2024-02-19 8:29 ` [PULL 31/49] ppc/pnv: Test pnv i2c master and connected devices Nicholas Piggin
2024-02-19 8:29 ` [PULL 32/49] hw/ppc: Add pnv nest pervasive common chiplet model Nicholas Piggin
2024-02-19 8:29 ` [PULL 33/49] hw/ppc: Add N1 " Nicholas Piggin
2024-02-19 8:29 ` [PULL 34/49] hw/ppc: N1 chiplet wiring Nicholas Piggin
2024-02-19 8:29 ` [PULL 35/49] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-02-19 8:29 ` [PULL 36/49] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-02-19 8:29 ` [PULL 37/49] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-02-19 8:29 ` [PULL 38/49] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2024-02-19 8:29 ` [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model Nicholas Piggin
2024-02-19 8:29 ` [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Nicholas Piggin
2024-02-19 8:29 ` [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-02-19 8:29 ` [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-02-19 8:29 ` [PULL 43/49] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-02-19 8:29 ` [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps Nicholas Piggin
2024-02-19 8:29 ` [PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing Nicholas Piggin
2024-02-19 8:29 ` [PULL 46/49] target/ppc: 4xx don't flush TLB for a newly written software TLB entry Nicholas Piggin
2024-02-19 8:29 ` [PULL 47/49] target/ppc: 4xx optimise tlbwe_lo TLB flushing Nicholas Piggin
2024-02-19 8:29 ` [PULL 48/49] target/ppc: 440 optimise tlbwe " Nicholas Piggin
2024-02-19 8:29 ` [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing Nicholas Piggin
2024-02-19 17:06 ` [PULL 00/49] ppc-for-9.0 queue Peter Maydell
2024-02-20 1:15 ` Nicholas Piggin
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