* [PATCH v4 1/3] hw/cxl/cxl-mailbox-utils: Add support for feature commands (8.2.9.6)
2024-02-19 15:00 [PATCH v4 0/3] hw/cxl/cxl-mailbox-utils: Add feature commands, device patrol scrub control and DDR5 ECS control features shiju.jose--- via
@ 2024-02-19 15:00 ` shiju.jose--- via
2024-02-19 16:38 ` Jonathan Cameron via
2024-02-19 15:00 ` [PATCH v4 2/3] hw/cxl/cxl-mailbox-utils: Add device patrol scrub control feature shiju.jose--- via
2024-02-19 15:00 ` [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS " shiju.jose--- via
2 siblings, 1 reply; 8+ messages in thread
From: shiju.jose--- via @ 2024-02-19 15:00 UTC (permalink / raw)
To: qemu-devel, linux-cxl
Cc: jonathan.cameron, tanxiaofei, prime.zeng, linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
Get Supported Features retrieves the list of supported device specific
features. The settings of a feature can be retrieved using Get Feature and
optionally modified using Set Feature.
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 175 +++++++++++++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 80a80f1ec2..779ce80e3c 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -66,6 +66,10 @@ enum {
LOGS = 0x04,
#define GET_SUPPORTED 0x0
#define GET_LOG 0x1
+ FEATURES = 0x05,
+ #define GET_SUPPORTED 0x0
+ #define GET_FEATURE 0x1
+ #define SET_FEATURE 0x2
IDENTIFY = 0x40,
#define MEMORY_DEVICE 0x0
CCLS = 0x41,
@@ -965,6 +969,165 @@ static CXLRetCode cmd_logs_get_log(const struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+/* CXL r3.1 section 8.2.9.6: Features */
+/*
+ * Get Supported Features output payload
+ * CXL r3.1 section 8.2.9.6.1 Table 8-96
+ */
+typedef struct CXLSupportedFeatureHeader {
+ uint16_t entries;
+ uint16_t nsuppfeats_dev;
+ uint32_t reserved;
+} QEMU_PACKED CXLSupportedFeatureHeader;
+
+/*
+ * Get Supported Features Supported Feature Entry
+ * CXL r3.1 section 8.2.9.6.1 Table 8-97
+ */
+typedef struct CXLSupportedFeatureEntry {
+ QemuUUID uuid;
+ uint16_t feat_index;
+ uint16_t get_feat_size;
+ uint16_t set_feat_size;
+ uint32_t attr_flags;
+ uint8_t get_feat_version;
+ uint8_t set_feat_version;
+ uint16_t set_feat_effects;
+ uint8_t rsvd[18];
+} QEMU_PACKED CXLSupportedFeatureEntry;
+
+enum CXL_SUPPORTED_FEATURES_LIST {
+ CXL_FEATURE_MAX
+};
+
+/* Get Feature CXL 3.1 Spec 8.2.9.6.2 */
+/*
+ * Get Feature input payload
+ * CXL r3.1 section 8.2.9.6.2 Table 8-99
+ */
+/* Get Feature : Payload in selection */
+enum CXL_GET_FEATURE_SELECTION {
+ CXL_GET_FEATURE_SEL_CURRENT_VALUE,
+ CXL_GET_FEATURE_SEL_DEFAULT_VALUE,
+ CXL_GET_FEATURE_SEL_SAVED_VALUE,
+ CXL_GET_FEATURE_SEL_MAX
+};
+
+/* Set Feature CXL 3.1 Spec 8.2.9.6.3 */
+/*
+ * Set Feature input payload
+ * CXL r3.1 section 8.2.9.6.3 Table 8-101
+ */
+typedef struct CXLSetFeatureInHeader {
+ QemuUUID uuid;
+ uint32_t flags;
+ uint16_t offset;
+ uint8_t version;
+ uint8_t rsvd[9];
+} QEMU_PACKED QEMU_ALIGNED(16) CXLSetFeatureInHeader;
+
+/* Set Feature : Payload in flags */
+#define CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MASK 0x7
+enum CXL_SET_FEATURE_FLAG_DATA_TRANSFER {
+ CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER,
+ CXL_SET_FEATURE_FLAG_INITIATE_DATA_TRANSFER,
+ CXL_SET_FEATURE_FLAG_CONTINUE_DATA_TRANSFER,
+ CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER,
+ CXL_SET_FEATURE_FLAG_ABORT_DATA_TRANSFER,
+ CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MAX
+};
+
+/* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
+static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
+ uint8_t *payload_in,
+ size_t len_in,
+ uint8_t *payload_out,
+ size_t *len_out,
+ CXLCCI *cci)
+{
+ struct {
+ uint32_t count;
+ uint16_t start_index;
+ uint16_t reserved;
+ } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_in = (void *)payload_in;
+
+ struct {
+ CXLSupportedFeatureHeader hdr;
+ CXLSupportedFeatureEntry feat_entries[];
+ } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_out = (void *)payload_out;
+ uint16_t index;
+ uint16_t entry, req_entries;
+ uint16_t feat_entries = 0;
+
+ if (get_feats_in->count < sizeof(CXLSupportedFeatureHeader) ||
+ get_feats_in->start_index > CXL_FEATURE_MAX) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ req_entries = (get_feats_in->count -
+ sizeof(CXLSupportedFeatureHeader)) /
+ sizeof(CXLSupportedFeatureEntry);
+ req_entries = MIN(req_entries, CXL_FEATURE_MAX);
+ index = get_feats_in->start_index;
+
+ entry = 0;
+ while (entry < req_entries) {
+ switch (index) {
+ default:
+ break;
+ }
+ index++;
+ entry++;
+ }
+
+ get_feats_out->hdr.nsuppfeats_dev = CXL_FEATURE_MAX;
+ get_feats_out->hdr.entries = feat_entries;
+ *len_out = sizeof(CXLSupportedFeatureHeader) +
+ feat_entries * sizeof(CXLSupportedFeatureEntry);
+
+ return CXL_MBOX_SUCCESS;
+}
+
+/* CXL r3.1 section 8.2.9.6.2: Get Feature (Opcode 0501h) */
+static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
+ uint8_t *payload_in,
+ size_t len_in,
+ uint8_t *payload_out,
+ size_t *len_out,
+ CXLCCI *cci)
+{
+ struct {
+ QemuUUID uuid;
+ uint16_t offset;
+ uint16_t count;
+ uint8_t selection;
+ } QEMU_PACKED QEMU_ALIGNED(16) * get_feature;
+ uint16_t bytes_to_copy = 0;
+
+ get_feature = (void *)payload_in;
+
+ if (get_feature->selection != CXL_GET_FEATURE_SEL_CURRENT_VALUE) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+ if (get_feature->offset + get_feature->count > cci->payload_max) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+
+ *len_out = bytes_to_copy;
+
+ return CXL_MBOX_SUCCESS;
+}
+
+/* CXL r3.1 section 8.2.9.6.3: Set Feature (Opcode 0502h) */
+static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
+ uint8_t *payload_in,
+ size_t len_in,
+ uint8_t *payload_out,
+ size_t *len_out,
+ CXLCCI *cci)
+{
+ return CXL_MBOX_SUCCESS;
+}
+
/* CXL r3.1 Section 8.2.9.9.1.1: Identify Memory Device (Opcode 4000h) */
static CXLRetCode cmd_identify_memory_device(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -2166,6 +2329,18 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = {
[LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported,
0, 0 },
[LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
+ [FEATURES][GET_SUPPORTED] = { "FEATURES_GET_SUPPORTED",
+ cmd_features_get_supported, 0x8, 0 },
+ [FEATURES][GET_FEATURE] = { "FEATURES_GET_FEATURE",
+ cmd_features_get_feature, 0x15, 0 },
+ [FEATURES][SET_FEATURE] = { "FEATURES_SET_FEATURE",
+ cmd_features_set_feature,
+ ~0,
+ (CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |
+ CXL_MBOX_IMMEDIATE_DATA_CHANGE |
+ CXL_MBOX_IMMEDIATE_POLICY_CHANGE |
+ CXL_MBOX_IMMEDIATE_LOG_CHANGE |
+ CXL_MBOX_SECURITY_STATE_CHANGE)},
[IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
cmd_identify_memory_device, 0, 0 },
[CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 1/3] hw/cxl/cxl-mailbox-utils: Add support for feature commands (8.2.9.6)
2024-02-19 15:00 ` [PATCH v4 1/3] hw/cxl/cxl-mailbox-utils: Add support for feature commands (8.2.9.6) shiju.jose--- via
@ 2024-02-19 16:38 ` Jonathan Cameron via
0 siblings, 0 replies; 8+ messages in thread
From: Jonathan Cameron via @ 2024-02-19 16:38 UTC (permalink / raw)
To: shiju.jose; +Cc: qemu-devel, linux-cxl, tanxiaofei, prime.zeng, linuxarm
On Mon, 19 Feb 2024 23:00:23 +0800
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
> CXL devices supports features with changeable attributes.
> Get Supported Features retrieves the list of supported device specific
> features. The settings of a feature can be retrieved using Get Feature and
> optionally modified using Set Feature.
>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Hi Shiju,
Sorry I've taken so long to get to this!
Looks good. One small comment inline.
Jonathan
> +
> +/* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
> +static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> + uint8_t *payload_in,
> + size_t len_in,
> + uint8_t *payload_out,
> + size_t *len_out,
> + CXLCCI *cci)
> +{
> + struct {
> + uint32_t count;
> + uint16_t start_index;
> + uint16_t reserved;
> + } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_in = (void *)payload_in;
> +
> + struct {
> + CXLSupportedFeatureHeader hdr;
> + CXLSupportedFeatureEntry feat_entries[];
> + } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_out = (void *)payload_out;
> + uint16_t index;
> + uint16_t entry, req_entries;
> + uint16_t feat_entries = 0;
> +
> + if (get_feats_in->count < sizeof(CXLSupportedFeatureHeader) ||
> + get_feats_in->start_index > CXL_FEATURE_MAX) {
> + return CXL_MBOX_INVALID_INPUT;
> + }
> + req_entries = (get_feats_in->count -
> + sizeof(CXLSupportedFeatureHeader)) /
> + sizeof(CXLSupportedFeatureEntry);
I'm struggling a bit with the Specification text.
I says that count is
"Count in bytes of the supported Feature data to return in the
output payload."
I suppose that includes the header but it's not entirely clear
to me. Let's go with what we have here unless we get a spec
clarification.
> + req_entries = MIN(req_entries, CXL_FEATURE_MAX);
> + index = get_feats_in->start_index;
> +
> + entry = 0;
> + while (entry < req_entries) {
Given it's a known set of bounds a for loops should be
easier to read.
for (index = get_feats_in->start_index;
index < req_entries;
index++) {
switch (index) {
default:
__builtin_unreachable();
}
}
> + switch (index) {
> + default:
> + break;
> + }
> + index++;
> + entry++;
> + }
> +
> + get_feats_out->hdr.nsuppfeats_dev = CXL_FEATURE_MAX;
> + get_feats_out->hdr.entries = feat_entries;
> + *len_out = sizeof(CXLSupportedFeatureHeader) +
> + feat_entries * sizeof(CXLSupportedFeatureEntry);
> +
> + return CXL_MBOX_SUCCESS;
> +}
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/3] hw/cxl/cxl-mailbox-utils: Add device patrol scrub control feature
2024-02-19 15:00 [PATCH v4 0/3] hw/cxl/cxl-mailbox-utils: Add feature commands, device patrol scrub control and DDR5 ECS control features shiju.jose--- via
2024-02-19 15:00 ` [PATCH v4 1/3] hw/cxl/cxl-mailbox-utils: Add support for feature commands (8.2.9.6) shiju.jose--- via
@ 2024-02-19 15:00 ` shiju.jose--- via
2024-02-19 16:49 ` Jonathan Cameron via
2024-02-19 15:00 ` [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS " shiju.jose--- via
2 siblings, 1 reply; 8+ messages in thread
From: shiju.jose--- via @ 2024-02-19 15:00 UTC (permalink / raw)
To: qemu-devel, linux-cxl
Cc: jonathan.cameron, tanxiaofei, prime.zeng, linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patrol scrub control allows the requester to specify the number of
hours for which the patrol scrub cycles must be completed, provided that
the requested number is not less than the minimum number of hours for the
patrol scrub cycle that the device is capable of. In addition, the patrol
scrub controls allow the host to disable and enable the feature in case
disabling of the feature is needed for other purposes such as
performance-aware operations which require the background operations to be
turned off.
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 97 +++++++++++++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 779ce80e3c..908ce16642 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -997,6 +997,7 @@ typedef struct CXLSupportedFeatureEntry {
} QEMU_PACKED CXLSupportedFeatureEntry;
enum CXL_SUPPORTED_FEATURES_LIST {
+ CXL_FEATURE_PATROL_SCRUB = 0,
CXL_FEATURE_MAX
};
@@ -1037,6 +1038,38 @@ enum CXL_SET_FEATURE_FLAG_DATA_TRANSFER {
CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MAX
};
+/* CXL r3.1 section 8.2.9.9.11.1: Device Patrol Scrub Control Feature */
+static const QemuUUID patrol_scrub_uuid = {
+ .data = UUID(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33,
+ 0x75, 0x77, 0x4e, 0x06, 0xdb, 0x8a)
+};
+
+#define CXL_MEMDEV_PS_GET_FEATURE_VERSION 0x01
+#define CXL_MEMDEV_PS_SET_FEATURE_VERSION 0x01
+#define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT BIT(0)
+#define CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT BIT(1)
+#define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT 12
+#define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT 1
+#define CXL_MEMDEV_PS_ENABLE_DEFAULT 0
+
+/* CXL memdev patrol scrub control attributes */
+typedef struct CXLMemPatrolScrubReadAttrs {
+ uint8_t scrub_cycle_cap;
+ uint16_t scrub_cycle;
+ uint8_t scrub_flags;
+} QEMU_PACKED CXLMemPatrolScrubReadAttrs;
+
+typedef struct CXLMemPatrolScrubWriteAttrs {
+ uint8_t scrub_cycle_hr;
+ uint8_t scrub_flags;
+} QEMU_PACKED CXLMemPatrolScrubWriteAttrs;
+
+typedef struct CXLMemPatrolScrubSetFeature {
+ CXLSetFeatureInHeader hdr;
+ CXLMemPatrolScrubWriteAttrs feat_data;
+} QEMU_PACKED QEMU_ALIGNED(16) CXLMemPatrolScrubSetFeature;
+static CXLMemPatrolScrubReadAttrs cxl_memdev_ps_feat_attrs;
+
/* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -1060,7 +1093,7 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
uint16_t feat_entries = 0;
if (get_feats_in->count < sizeof(CXLSupportedFeatureHeader) ||
- get_feats_in->start_index > CXL_FEATURE_MAX) {
+ get_feats_in->start_index >= CXL_FEATURE_MAX) {
return CXL_MBOX_INVALID_INPUT;
}
req_entries = (get_feats_in->count -
@@ -1072,6 +1105,31 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
entry = 0;
while (entry < req_entries) {
switch (index) {
+ case CXL_FEATURE_PATROL_SCRUB:
+ /* Fill supported feature entry for device patrol scrub control */
+ get_feats_out->feat_entries[entry] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = patrol_scrub_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemPatrolScrubReadAttrs),
+ .set_feat_size = sizeof(CXLMemPatrolScrubWriteAttrs),
+ /* Bit[0] : 1, feature attributes changeable */
+ .attr_flags = 0x1,
+ .get_feat_version = CXL_MEMDEV_PS_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_PS_SET_FEATURE_VERSION,
+ .set_feat_effects = 0,
+ };
+ feat_entries++;
+ /* Set default value for device patrol scrub read attributes */
+ cxl_memdev_ps_feat_attrs.scrub_cycle_cap =
+ CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT |
+ CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT;
+ cxl_memdev_ps_feat_attrs.scrub_cycle =
+ CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT |
+ (CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT << 8);
+ cxl_memdev_ps_feat_attrs.scrub_flags =
+ CXL_MEMDEV_PS_ENABLE_DEFAULT;
+ break;
default:
break;
}
@@ -1112,6 +1170,20 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
return CXL_MBOX_INVALID_INPUT;
}
+ if (qemu_uuid_is_equal(&get_feature->uuid, &patrol_scrub_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemPatrolScrubReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemPatrolScrubReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ &cxl_memdev_ps_feat_attrs + get_feature->offset,
+ bytes_to_copy);
+ } else {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
*len_out = bytes_to_copy;
return CXL_MBOX_SUCCESS;
@@ -1125,6 +1197,29 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
size_t *len_out,
CXLCCI *cci)
{
+ CXLMemPatrolScrubWriteAttrs *ps_write_attrs;
+ CXLMemPatrolScrubSetFeature *ps_set_feature;
+ CXLSetFeatureInHeader *hdr = (void *)payload_in;
+
+ if (qemu_uuid_is_equal(&hdr->uuid, &patrol_scrub_uuid)) {
+ if (hdr->version != CXL_MEMDEV_PS_SET_FEATURE_VERSION ||
+ (hdr->flags & CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MASK) !=
+ CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ ps_set_feature = (void *)payload_in;
+ ps_write_attrs = &ps_set_feature->feat_data;
+ cxl_memdev_ps_feat_attrs.scrub_cycle &= ~0xFF;
+ cxl_memdev_ps_feat_attrs.scrub_cycle |=
+ ps_write_attrs->scrub_cycle_hr & 0xFF;
+ cxl_memdev_ps_feat_attrs.scrub_flags &= ~0x1;
+ cxl_memdev_ps_feat_attrs.scrub_flags |=
+ ps_write_attrs->scrub_flags & 0x1;
+ } else {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
return CXL_MBOX_SUCCESS;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/3] hw/cxl/cxl-mailbox-utils: Add device patrol scrub control feature
2024-02-19 15:00 ` [PATCH v4 2/3] hw/cxl/cxl-mailbox-utils: Add device patrol scrub control feature shiju.jose--- via
@ 2024-02-19 16:49 ` Jonathan Cameron via
0 siblings, 0 replies; 8+ messages in thread
From: Jonathan Cameron via @ 2024-02-19 16:49 UTC (permalink / raw)
To: shiju.jose; +Cc: qemu-devel, linux-cxl, tanxiaofei, prime.zeng, linuxarm
On Mon, 19 Feb 2024 23:00:24 +0800
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
> feature. The device patrol scrub proactively locates and makes corrections
> to errors in regular cycle. The patrol scrub control allows the request to
> configure patrol scrub input configurations.
>
> The patrol scrub control allows the requester to specify the number of
> hours for which the patrol scrub cycles must be completed, provided that
> the requested number is not less than the minimum number of hours for the
> patrol scrub cycle that the device is capable of. In addition, the patrol
> scrub controls allow the host to disable and enable the feature in case
> disabling of the feature is needed for other purposes such as
> performance-aware operations which require the background operations to be
> turned off.
>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
The data can't be global as we need to have separate controls per CXL type3
device so that each instance can have different settings.
Otherwise a few minor comments inline.
Jonathan
> ---
> hw/cxl/cxl-mailbox-utils.c | 97 +++++++++++++++++++++++++++++++++++++-
> 1 file changed, 96 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 779ce80e3c..908ce16642 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -997,6 +997,7 @@ typedef struct CXLSupportedFeatureEntry {
> } QEMU_PACKED CXLSupportedFeatureEntry;
>
> enum CXL_SUPPORTED_FEATURES_LIST {
> + CXL_FEATURE_PATROL_SCRUB = 0,
> CXL_FEATURE_MAX
> };
>
> @@ -1037,6 +1038,38 @@ enum CXL_SET_FEATURE_FLAG_DATA_TRANSFER {
> CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MAX
> };
>
> +/* CXL r3.1 section 8.2.9.9.11.1: Device Patrol Scrub Control Feature */
> +static const QemuUUID patrol_scrub_uuid = {
> + .data = UUID(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33,
> + 0x75, 0x77, 0x4e, 0x06, 0xdb, 0x8a)
> +};
> +
> +#define CXL_MEMDEV_PS_GET_FEATURE_VERSION 0x01
> +#define CXL_MEMDEV_PS_SET_FEATURE_VERSION 0x01
> +#define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT BIT(0)
> +#define CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT BIT(1)
> +#define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT 12
> +#define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT 1
> +#define CXL_MEMDEV_PS_ENABLE_DEFAULT 0
> +
> +/* CXL memdev patrol scrub control attributes */
> +typedef struct CXLMemPatrolScrubReadAttrs {
> + uint8_t scrub_cycle_cap;
> + uint16_t scrub_cycle;
> + uint8_t scrub_flags;
> +} QEMU_PACKED CXLMemPatrolScrubReadAttrs;
> +
> +typedef struct CXLMemPatrolScrubWriteAttrs {
> + uint8_t scrub_cycle_hr;
> + uint8_t scrub_flags;
> +} QEMU_PACKED CXLMemPatrolScrubWriteAttrs;
> +
> +typedef struct CXLMemPatrolScrubSetFeature {
> + CXLSetFeatureInHeader hdr;
> + CXLMemPatrolScrubWriteAttrs feat_data;
> +} QEMU_PACKED QEMU_ALIGNED(16) CXLMemPatrolScrubSetFeature;
> +static CXLMemPatrolScrubReadAttrs cxl_memdev_ps_feat_attrs;
> +
> /* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
> static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> uint8_t *payload_in,
> @@ -1060,7 +1093,7 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> uint16_t feat_entries = 0;
>
> if (get_feats_in->count < sizeof(CXLSupportedFeatureHeader) ||
> - get_feats_in->start_index > CXL_FEATURE_MAX) {
> + get_feats_in->start_index >= CXL_FEATURE_MAX) {
Change looks valid, but should have been in patch 1.
> return CXL_MBOX_INVALID_INPUT;
> }
> req_entries = (get_feats_in->count -
> @@ -1072,6 +1105,31 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> entry = 0;
> while (entry < req_entries) {
> switch (index) {
> + case CXL_FEATURE_PATROL_SCRUB:
> + /* Fill supported feature entry for device patrol scrub control */
> + get_feats_out->feat_entries[entry] =
> + (struct CXLSupportedFeatureEntry) {
> + .uuid = patrol_scrub_uuid,
> + .feat_index = index,
> + .get_feat_size = sizeof(CXLMemPatrolScrubReadAttrs),
> + .set_feat_size = sizeof(CXLMemPatrolScrubWriteAttrs),
> + /* Bit[0] : 1, feature attributes changeable */
> + .attr_flags = 0x1,
> + .get_feat_version = CXL_MEMDEV_PS_GET_FEATURE_VERSION,
> + .set_feat_version = CXL_MEMDEV_PS_SET_FEATURE_VERSION,
> + .set_feat_effects = 0,
> + };
> + feat_entries++;
> + /* Set default value for device patrol scrub read attributes */
> + cxl_memdev_ps_feat_attrs.scrub_cycle_cap =
> + CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT |
> + CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT;
> + cxl_memdev_ps_feat_attrs.scrub_cycle =
> + CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT |
> + (CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT << 8);
> + cxl_memdev_ps_feat_attrs.scrub_flags =
> + CXL_MEMDEV_PS_ENABLE_DEFAULT;
This is general defaults setup - doesn't belong here.
Not strictly necessary for a driver to have called the query for supported
features before trying to use them.
Move this to mem/cxl_type3.c as part of the device emulation.
> + break;
> default:
> break;
> }
> @@ -1112,6 +1170,20 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
> return CXL_MBOX_INVALID_INPUT;
> }
>
> + if (qemu_uuid_is_equal(&get_feature->uuid, &patrol_scrub_uuid)) {
> + if (get_feature->offset >= sizeof(CXLMemPatrolScrubReadAttrs)) {
> + return CXL_MBOX_INVALID_INPUT;
> + }
> + bytes_to_copy = sizeof(CXLMemPatrolScrubReadAttrs) -
> + get_feature->offset;
> + bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
> + memcpy(payload_out,
> + &cxl_memdev_ps_feat_attrs + get_feature->offset,
> + bytes_to_copy);
> + } else {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> *len_out = bytes_to_copy;
>
> return CXL_MBOX_SUCCESS;
> @@ -1125,6 +1197,29 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
> size_t *len_out,
> CXLCCI *cci)
> {
> + CXLMemPatrolScrubWriteAttrs *ps_write_attrs;
> + CXLMemPatrolScrubSetFeature *ps_set_feature;
> + CXLSetFeatureInHeader *hdr = (void *)payload_in;
> +
> + if (qemu_uuid_is_equal(&hdr->uuid, &patrol_scrub_uuid)) {
> + if (hdr->version != CXL_MEMDEV_PS_SET_FEATURE_VERSION ||
> + (hdr->flags & CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MASK) !=
> + CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER) {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> + ps_set_feature = (void *)payload_in;
> + ps_write_attrs = &ps_set_feature->feat_data;
> + cxl_memdev_ps_feat_attrs.scrub_cycle &= ~0xFF;
This needed to be embedded in the Type 3 device structures - not globally shared.
You'll need to check the device type, then convert cci->d to it.
if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_TYPE3)) {
CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
Add the feature attrs to that structure (as for now it's type 3 specific and
we don't have a generalized place for memory features beyond that).
> + cxl_memdev_ps_feat_attrs.scrub_cycle |=
> + ps_write_attrs->scrub_cycle_hr & 0xFF;
> + cxl_memdev_ps_feat_attrs.scrub_flags &= ~0x1;
> + cxl_memdev_ps_feat_attrs.scrub_flags |=
> + ps_write_attrs->scrub_flags & 0x1;
> + } else {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> return CXL_MBOX_SUCCESS;
> }
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control feature
2024-02-19 15:00 [PATCH v4 0/3] hw/cxl/cxl-mailbox-utils: Add feature commands, device patrol scrub control and DDR5 ECS control features shiju.jose--- via
2024-02-19 15:00 ` [PATCH v4 1/3] hw/cxl/cxl-mailbox-utils: Add support for feature commands (8.2.9.6) shiju.jose--- via
2024-02-19 15:00 ` [PATCH v4 2/3] hw/cxl/cxl-mailbox-utils: Add device patrol scrub control feature shiju.jose--- via
@ 2024-02-19 15:00 ` shiju.jose--- via
2024-02-19 16:59 ` Jonathan Cameron via
2 siblings, 1 reply; 8+ messages in thread
From: shiju.jose--- via @ 2024-02-19 15:00 UTC (permalink / raw)
To: qemu-devel, linux-cxl
Cc: jonathan.cameron, tanxiaofei, prime.zeng, linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected data bits to the DRAM array
while providing transparency to error counts. The ECS control feature
allows the request to configure ECS input configurations during system
boot or at run-time.
The ECS control allows the requester to change the log entry type, the ECS
threshold count provided that the request is within the definition
specified in DDR5 mode registers, change mode between codeword mode and
row count mode, and reset the ECS counter.
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 100 ++++++++++++++++++++++++++++++++++++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 908ce16642..2277418c07 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -998,6 +998,7 @@ typedef struct CXLSupportedFeatureEntry {
enum CXL_SUPPORTED_FEATURES_LIST {
CXL_FEATURE_PATROL_SCRUB = 0,
+ CXL_FEATURE_ECS,
CXL_FEATURE_MAX
};
@@ -1070,6 +1071,43 @@ typedef struct CXLMemPatrolScrubSetFeature {
} QEMU_PACKED QEMU_ALIGNED(16) CXLMemPatrolScrubSetFeature;
static CXLMemPatrolScrubReadAttrs cxl_memdev_ps_feat_attrs;
+/*
+ * CXL r3.1 section 8.2.9.9.11.2:
+ * DDR5 Error Check Scrub (ECS) Control Feature
+ */
+static const QemuUUID ecs_uuid = {
+ .data = UUID(0xe5b13f22, 0x2328, 0x4a14, 0xb8, 0xba,
+ 0xb9, 0x69, 0x1e, 0x89, 0x33, 0x86)
+};
+
+#define CXL_ECS_GET_FEATURE_VERSION 0x01
+#define CXL_ECS_SET_FEATURE_VERSION 0x01
+#define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT 0x01
+#define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT 1
+#define CXL_ECS_THRESHOLD_COUNT_DEFAULT 3 /* 3: 256, 4: 1024, 5: 4096 */
+#define CXL_ECS_MODE_DEFAULT 0
+
+#define CXL_ECS_NUM_MEDIA_FRUS 3
+
+/* CXL memdev DDR5 ECS control attributes */
+typedef struct CXLMemECSReadAttrs {
+ uint8_t ecs_log_cap;
+ uint8_t ecs_cap;
+ uint16_t ecs_config;
+ uint8_t ecs_flags;
+} QEMU_PACKED CXLMemECSReadAttrs;
+
+typedef struct CXLMemECSWriteAttrs {
+ uint8_t ecs_log_cap;
+ uint16_t ecs_config;
+} QEMU_PACKED CXLMemECSWriteAttrs;
+
+typedef struct CXLMemECSSetFeature {
+ CXLSetFeatureInHeader hdr;
+ CXLMemECSWriteAttrs feat_data[];
+} QEMU_PACKED QEMU_ALIGNED(16) CXLMemECSSetFeature;
+static CXLMemECSReadAttrs cxl_ecs_feat_attrs[CXL_ECS_NUM_MEDIA_FRUS];
+
/* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -1088,7 +1126,7 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
CXLSupportedFeatureHeader hdr;
CXLSupportedFeatureEntry feat_entries[];
} QEMU_PACKED QEMU_ALIGNED(16) * get_feats_out = (void *)payload_out;
- uint16_t index;
+ uint16_t count, index;
uint16_t entry, req_entries;
uint16_t feat_entries = 0;
@@ -1130,6 +1168,35 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
cxl_memdev_ps_feat_attrs.scrub_flags =
CXL_MEMDEV_PS_ENABLE_DEFAULT;
break;
+ case CXL_FEATURE_ECS:
+ /* Fill supported feature entry for device DDR5 ECS control */
+ get_feats_out->feat_entries[entry] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = ecs_uuid,
+ .feat_index = index,
+ .get_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
+ sizeof(CXLMemECSReadAttrs),
+ .set_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
+ sizeof(CXLMemECSWriteAttrs),
+ .attr_flags = 0x1,
+ .get_feat_version = CXL_ECS_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_ECS_SET_FEATURE_VERSION,
+ .set_feat_effects = 0,
+ };
+ feat_entries++;
+ /* Set default value for DDR5 ECS read attributes */
+ for (count = 0; count < CXL_ECS_NUM_MEDIA_FRUS; count++) {
+ cxl_ecs_feat_attrs[count].ecs_log_cap =
+ CXL_ECS_LOG_ENTRY_TYPE_DEFAULT;
+ cxl_ecs_feat_attrs[count].ecs_cap =
+ CXL_ECS_REALTIME_REPORT_CAP_DEFAULT;
+ cxl_ecs_feat_attrs[count].ecs_config =
+ CXL_ECS_THRESHOLD_COUNT_DEFAULT |
+ (CXL_ECS_MODE_DEFAULT << 3);
+ /* Reserved */
+ cxl_ecs_feat_attrs[count].ecs_flags = 0;
+ }
+ break;
default:
break;
}
@@ -1180,6 +1247,18 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
memcpy(payload_out,
&cxl_memdev_ps_feat_attrs + get_feature->offset,
bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &ecs_uuid)) {
+ if (get_feature->offset >= CXL_ECS_NUM_MEDIA_FRUS *
+ sizeof(CXLMemECSReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = CXL_ECS_NUM_MEDIA_FRUS *
+ sizeof(CXLMemECSReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ &cxl_ecs_feat_attrs + get_feature->offset,
+ bytes_to_copy);
} else {
return CXL_MBOX_UNSUPPORTED;
}
@@ -1197,8 +1276,11 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
size_t *len_out,
CXLCCI *cci)
{
+ uint16_t count;
CXLMemPatrolScrubWriteAttrs *ps_write_attrs;
+ CXLMemECSWriteAttrs *ecs_write_attrs;
CXLMemPatrolScrubSetFeature *ps_set_feature;
+ CXLMemECSSetFeature *ecs_set_feature;
CXLSetFeatureInHeader *hdr = (void *)payload_in;
if (qemu_uuid_is_equal(&hdr->uuid, &patrol_scrub_uuid)) {
@@ -1216,6 +1298,22 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
cxl_memdev_ps_feat_attrs.scrub_flags &= ~0x1;
cxl_memdev_ps_feat_attrs.scrub_flags |=
ps_write_attrs->scrub_flags & 0x1;
+ } else if (qemu_uuid_is_equal(&hdr->uuid,
+ &ecs_uuid)) {
+ if (hdr->version != CXL_ECS_SET_FEATURE_VERSION ||
+ (hdr->flags & CXL_SET_FEATURE_FLAG_DATA_TRANSFER_MASK) !=
+ CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ ecs_set_feature = (void *)payload_in;
+ ecs_write_attrs = ecs_set_feature->feat_data;
+ for (count = 0; count < CXL_ECS_NUM_MEDIA_FRUS; count++) {
+ cxl_ecs_feat_attrs[count].ecs_log_cap =
+ ecs_write_attrs[count].ecs_log_cap;
+ cxl_ecs_feat_attrs[count].ecs_config =
+ ecs_write_attrs[count].ecs_config & 0x1F;
+ }
} else {
return CXL_MBOX_UNSUPPORTED;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control feature
2024-02-19 15:00 ` [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS " shiju.jose--- via
@ 2024-02-19 16:59 ` Jonathan Cameron via
2024-02-19 17:46 ` Shiju Jose via
0 siblings, 1 reply; 8+ messages in thread
From: Jonathan Cameron via @ 2024-02-19 16:59 UTC (permalink / raw)
To: shiju.jose; +Cc: qemu-devel, linux-cxl, tanxiaofei, prime.zeng, linuxarm
On Mon, 19 Feb 2024 23:00:25 +0800
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.
>
> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
> Specification (JESD79-5) and allows the DRAM to internally read, correct
> single-bit errors, and write back corrected data bits to the DRAM array
> while providing transparency to error counts. The ECS control feature
> allows the request to configure ECS input configurations during system
> boot or at run-time.
>
> The ECS control allows the requester to change the log entry type, the ECS
> threshold count provided that the request is within the definition
> specified in DDR5 mode registers, change mode between codeword mode and
> row count mode, and reset the ECS counter.
>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Same thing about it being per device, not global.
Otherwise, just a few minor comments inline.
> ---
> hw/cxl/cxl-mailbox-utils.c | 100 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 99 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 908ce16642..2277418c07 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -998,6 +998,7 @@ typedef struct CXLSupportedFeatureEntry {
>
> enum CXL_SUPPORTED_FEATURES_LIST {
> CXL_FEATURE_PATROL_SCRUB = 0,
> + CXL_FEATURE_ECS,
> CXL_FEATURE_MAX
> };
>
> @@ -1070,6 +1071,43 @@ typedef struct CXLMemPatrolScrubSetFeature {
> } QEMU_PACKED QEMU_ALIGNED(16) CXLMemPatrolScrubSetFeature;
> static CXLMemPatrolScrubReadAttrs cxl_memdev_ps_feat_attrs;
>
> +/*
> + * CXL r3.1 section 8.2.9.9.11.2:
> + * DDR5 Error Check Scrub (ECS) Control Feature
> + */
> +static const QemuUUID ecs_uuid = {
> + .data = UUID(0xe5b13f22, 0x2328, 0x4a14, 0xb8, 0xba,
> + 0xb9, 0x69, 0x1e, 0x89, 0x33, 0x86)
> +};
> +
> +#define CXL_ECS_GET_FEATURE_VERSION 0x01
> +#define CXL_ECS_SET_FEATURE_VERSION 0x01
> +#define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT 0x01
> +#define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT 1
> +#define CXL_ECS_THRESHOLD_COUNT_DEFAULT 3 /* 3: 256, 4: 1024, 5: 4096 */
> +#define CXL_ECS_MODE_DEFAULT 0
> +
> +#define CXL_ECS_NUM_MEDIA_FRUS 3
> +
> +/* CXL memdev DDR5 ECS control attributes */
> +typedef struct CXLMemECSReadAttrs {
> + uint8_t ecs_log_cap;
> + uint8_t ecs_cap;
> + uint16_t ecs_config;
> + uint8_t ecs_flags;
> +} QEMU_PACKED CXLMemECSReadAttrs;
> +
> +typedef struct CXLMemECSWriteAttrs {
> + uint8_t ecs_log_cap;
> + uint16_t ecs_config;
> +} QEMU_PACKED CXLMemECSWriteAttrs;
> +
> +typedef struct CXLMemECSSetFeature {
> + CXLSetFeatureInHeader hdr;
> + CXLMemECSWriteAttrs feat_data[];
> +} QEMU_PACKED QEMU_ALIGNED(16) CXLMemECSSetFeature;
> +static CXLMemECSReadAttrs cxl_ecs_feat_attrs[CXL_ECS_NUM_MEDIA_FRUS];
This should be device instance specific.
> +
> /* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
> static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> uint8_t *payload_in,
> @@ -1088,7 +1126,7 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> CXLSupportedFeatureHeader hdr;
> CXLSupportedFeatureEntry feat_entries[];
> } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_out = (void *)payload_out;
> - uint16_t index;
> + uint16_t count, index;
> uint16_t entry, req_entries;
> uint16_t feat_entries = 0;
>
> @@ -1130,6 +1168,35 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
> cxl_memdev_ps_feat_attrs.scrub_flags =
> CXL_MEMDEV_PS_ENABLE_DEFAULT;
> break;
> + case CXL_FEATURE_ECS:
> + /* Fill supported feature entry for device DDR5 ECS control */
> + get_feats_out->feat_entries[entry] =
> + (struct CXLSupportedFeatureEntry) {
> + .uuid = ecs_uuid,
> + .feat_index = index,
> + .get_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
> + sizeof(CXLMemECSReadAttrs),
> + .set_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
> + sizeof(CXLMemECSWriteAttrs),
> + .attr_flags = 0x1,
> + .get_feat_version = CXL_ECS_GET_FEATURE_VERSION,
> + .set_feat_version = CXL_ECS_SET_FEATURE_VERSION,
> + .set_feat_effects = 0,
I think spec says Immediate config change for this one.Plus the CEL bit
should be set (bit 9)
Check this for the other features as well.
> + };
> + feat_entries++;
Why update this mid setting up the record? I briefly thought this wrote
two different records (which was odd!)
We don't have gaps in the features - we probably won't ever provide that
degree of control of the QEMU model, so feat_entries will be
req_entries - get_feats_in->start_index
No need to keep a count.
> + /* Set default value for DDR5 ECS read attributes */
> + for (count = 0; count < CXL_ECS_NUM_MEDIA_FRUS; count++) {
> + cxl_ecs_feat_attrs[count].ecs_log_cap =
> + CXL_ECS_LOG_ENTRY_TYPE_DEFAULT;
> + cxl_ecs_feat_attrs[count].ecs_cap =
> + CXL_ECS_REALTIME_REPORT_CAP_DEFAULT;
> + cxl_ecs_feat_attrs[count].ecs_config =
> + CXL_ECS_THRESHOLD_COUNT_DEFAULT |
> + (CXL_ECS_MODE_DEFAULT << 3);
> + /* Reserved */
> + cxl_ecs_feat_attrs[count].ecs_flags = 0;
> + }
> + break;
> default:
> break;
> }
^ permalink raw reply [flat|nested] 8+ messages in thread* RE: [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control feature
2024-02-19 16:59 ` Jonathan Cameron via
@ 2024-02-19 17:46 ` Shiju Jose via
0 siblings, 0 replies; 8+ messages in thread
From: Shiju Jose via @ 2024-02-19 17:46 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, tanxiaofei,
Zengtao (B), Linuxarm
Hi Jonathan,
Thanks for the feedbacks.
>-----Original Message-----
>From: Jonathan Cameron <jonathan.cameron@huawei.com>
>Sent: 19 February 2024 16:59
>To: Shiju Jose <shiju.jose@huawei.com>
>Cc: qemu-devel@nongnu.org; linux-cxl@vger.kernel.org; tanxiaofei
><tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>; Linuxarm
><linuxarm@huawei.com>
>Subject: Re: [PATCH v4 3/3] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS
>control feature
>
>On Mon, 19 Feb 2024 23:00:25 +0800
><shiju.jose@huawei.com> wrote:
>
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub
>> (ECS) control feature.
>>
>> The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
>> Specification (JESD79-5) and allows the DRAM to internally read,
>> correct single-bit errors, and write back corrected data bits to the
>> DRAM array while providing transparency to error counts. The ECS
>> control feature allows the request to configure ECS input
>> configurations during system boot or at run-time.
>>
>> The ECS control allows the requester to change the log entry type, the
>> ECS threshold count provided that the request is within the definition
>> specified in DDR5 mode registers, change mode between codeword mode
>> and row count mode, and reset the ECS counter.
>>
>> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
>> Reviewed-by: Fan Ni <fan.ni@samsung.com>
>> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>
>Same thing about it being per device, not global.
Sure. I will check this.
>
>Otherwise, just a few minor comments inline.
>
>> ---
>> hw/cxl/cxl-mailbox-utils.c | 100
>> ++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 99 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
>> index 908ce16642..2277418c07 100644
>> --- a/hw/cxl/cxl-mailbox-utils.c
>> +++ b/hw/cxl/cxl-mailbox-utils.c
>> @@ -998,6 +998,7 @@ typedef struct CXLSupportedFeatureEntry {
>>
>> enum CXL_SUPPORTED_FEATURES_LIST {
>> CXL_FEATURE_PATROL_SCRUB = 0,
>> + CXL_FEATURE_ECS,
>> CXL_FEATURE_MAX
>> };
>>
>> @@ -1070,6 +1071,43 @@ typedef struct CXLMemPatrolScrubSetFeature { }
>> QEMU_PACKED QEMU_ALIGNED(16) CXLMemPatrolScrubSetFeature; static
>> CXLMemPatrolScrubReadAttrs cxl_memdev_ps_feat_attrs;
>>
>> +/*
>> + * CXL r3.1 section 8.2.9.9.11.2:
>> + * DDR5 Error Check Scrub (ECS) Control Feature */ static const
>> +QemuUUID ecs_uuid = {
>> + .data = UUID(0xe5b13f22, 0x2328, 0x4a14, 0xb8, 0xba,
>> + 0xb9, 0x69, 0x1e, 0x89, 0x33, 0x86) };
>> +
>> +#define CXL_ECS_GET_FEATURE_VERSION 0x01
>> +#define CXL_ECS_SET_FEATURE_VERSION 0x01
>> +#define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT 0x01
>> +#define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT 1
>> +#define CXL_ECS_THRESHOLD_COUNT_DEFAULT 3 /* 3: 256, 4: 1024, 5:
>4096 */
>> +#define CXL_ECS_MODE_DEFAULT 0
>> +
>> +#define CXL_ECS_NUM_MEDIA_FRUS 3
>> +
>> +/* CXL memdev DDR5 ECS control attributes */ typedef struct
>> +CXLMemECSReadAttrs {
>> + uint8_t ecs_log_cap;
>> + uint8_t ecs_cap;
>> + uint16_t ecs_config;
>> + uint8_t ecs_flags;
>> +} QEMU_PACKED CXLMemECSReadAttrs;
>> +
>> +typedef struct CXLMemECSWriteAttrs {
>> + uint8_t ecs_log_cap;
>> + uint16_t ecs_config;
>> +} QEMU_PACKED CXLMemECSWriteAttrs;
>> +
>> +typedef struct CXLMemECSSetFeature {
>> + CXLSetFeatureInHeader hdr;
>> + CXLMemECSWriteAttrs feat_data[]; } QEMU_PACKED
>> +QEMU_ALIGNED(16) CXLMemECSSetFeature; static CXLMemECSReadAttrs
>> +cxl_ecs_feat_attrs[CXL_ECS_NUM_MEDIA_FRUS];
>
>This should be device instance specific.
Ok.
>
>> +
>> /* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h)
>> */ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd
>*cmd,
>> uint8_t *payload_in, @@
>> -1088,7 +1126,7 @@ static CXLRetCode cmd_features_get_supported(const
>struct cxl_cmd *cmd,
>> CXLSupportedFeatureHeader hdr;
>> CXLSupportedFeatureEntry feat_entries[];
>> } QEMU_PACKED QEMU_ALIGNED(16) * get_feats_out = (void
>*)payload_out;
>> - uint16_t index;
>> + uint16_t count, index;
>> uint16_t entry, req_entries;
>> uint16_t feat_entries = 0;
>>
>> @@ -1130,6 +1168,35 @@ static CXLRetCode
>cmd_features_get_supported(const struct cxl_cmd *cmd,
>> cxl_memdev_ps_feat_attrs.scrub_flags =
>> CXL_MEMDEV_PS_ENABLE_DEFAULT;
>> break;
>> + case CXL_FEATURE_ECS:
>> + /* Fill supported feature entry for device DDR5 ECS control */
>> + get_feats_out->feat_entries[entry] =
>> + (struct CXLSupportedFeatureEntry) {
>> + .uuid = ecs_uuid,
>> + .feat_index = index,
>> + .get_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
>> + sizeof(CXLMemECSReadAttrs),
>> + .set_feat_size = CXL_ECS_NUM_MEDIA_FRUS *
>> + sizeof(CXLMemECSWriteAttrs),
>> + .attr_flags = 0x1,
>> + .get_feat_version = CXL_ECS_GET_FEATURE_VERSION,
>> + .set_feat_version = CXL_ECS_SET_FEATURE_VERSION,
>> + .set_feat_effects = 0,
>I think spec says Immediate config change for this one.Plus the CEL bit should be
>set (bit 9)
Sure. I will change.
>
>Check this for the other features as well.
>
>> + };
>> + feat_entries++;
>
>Why update this mid setting up the record? I briefly thought this wrote two
>different records (which was odd!)
>
>We don't have gaps in the features - we probably won't ever provide that degree
>of control of the QEMU model, so feat_entries will be req_entries -
>get_feats_in->start_index No need to keep a count.
Yes. You are right.
>
>> + /* Set default value for DDR5 ECS read attributes */
>> + for (count = 0; count < CXL_ECS_NUM_MEDIA_FRUS; count++) {
>> + cxl_ecs_feat_attrs[count].ecs_log_cap =
>> + CXL_ECS_LOG_ENTRY_TYPE_DEFAULT;
>> + cxl_ecs_feat_attrs[count].ecs_cap =
>> + CXL_ECS_REALTIME_REPORT_CAP_DEFAULT;
>> + cxl_ecs_feat_attrs[count].ecs_config =
>> + CXL_ECS_THRESHOLD_COUNT_DEFAULT |
>> + (CXL_ECS_MODE_DEFAULT << 3);
>> + /* Reserved */
>> + cxl_ecs_feat_attrs[count].ecs_flags = 0;
>> + }
>> + break;
>> default:
>> break;
>> }
Thanks,
Shiju
^ permalink raw reply [flat|nested] 8+ messages in thread