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(cust-west-par-46-193-4-103.cust.wifirst.net [46.193.4.103]) by zproxy2.enst.fr (Postfix) with ESMTPSA id 4AA8780568; Mon, 19 Feb 2024 21:09:16 +0100 (CET) From: Arnaud Minier To: qemu-devel@nongnu.org Cc: Thomas Huth , Laurent Vivier , =?UTF-8?q?In=C3=A8s=20Varhol?= , Samuel Tardieu , qemu-arm@nongnu.org, Alistair Francis , Peter Maydell , Paolo Bonzini , Arnaud Minier Subject: [PATCH v5 0/8] Add device STM32L4x5 RCC Date: Mon, 19 Feb 2024 21:09:00 +0100 Message-Id: <20240219200908.49551-1-arnaud.minier@telecom-paris.fr> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2001:660:330f:2::dd; envelope-from=arnaud.minier@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds the STM32L4x5 RCC (Reset and Clock Control) device and is= part of a series implementing the STM32L4x5 with a few peripherals. Due to the high number of lines, I tried to split the patch into several = independent commits. Each commit compiles on its own but I had to add temporary workarounds in= intermediary commits to allow them to compile even if some functions are= not used. However, they have been removed once the functions were used. = Tell me if this is ok or if I should remove them. Also, the tests are not very exhaustive for the moment. I have not found = a way to test the clocks' frequency from the qtests, which limits severel= y the exhaustiveness of the tests. Thanks to Philippe Mathieu-Daud=C3=A9 and Luc Michel for guiding me towar= d the hw/misc/bcm2835_cprman.c implementation and answering my questions = about clock emulation in qemu ! Changes from v1 to v2: - Removed a mention in the tests - Added an early return to prevent a clang compilation error in rcc_updat= e_pllsaixcfgr() Changes from v2 to v3: - Changed the timeout method used in the tests - Added a real value for ICSR register - Replaced some TODOs with correct error handling - Added a commit that implements correct write protections for the CR reg= ister Changes from v3 to v4: - Rebased on top of current master - Implemented reset functions for the multiplexers and the PLLs - Added explanatory messages to every commit - Addded logs for unimplemented registers - Completed the VMState for the multiplexers and the PLLs Changes from v4 to v5: - Abort when trying to set an out-of-bound pll vco multiplier Arnaud Minier (8): Implement STM32L4x5_RCC skeleton Add an internal clock multiplexer object Add an internal PLL Clock object Add initialization information for PLLs and clock multiplexers RCC: Handle Register Updates Add write protections to CR register STM32L4x5: Use the RCC Sysclk Add tests for the STM32L4x5_RCC MAINTAINERS | 5 +- docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/arm/Kconfig | 1 + hw/arm/b-l475e-iot01a.c | 10 +- hw/arm/stm32l4x5_soc.c | 45 +- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/stm32l4x5_rcc.c | 1416 +++++++++++++++++++++ hw/misc/trace-events | 14 + include/hw/arm/stm32l4x5_soc.h | 5 +- include/hw/misc/stm32l4x5_rcc.h | 239 ++++ include/hw/misc/stm32l4x5_rcc_internals.h | 1042 +++++++++++++++ tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_rcc-test.c | 207 +++ 14 files changed, 2948 insertions(+), 45 deletions(-) create mode 100644 hw/misc/stm32l4x5_rcc.c create mode 100644 include/hw/misc/stm32l4x5_rcc.h create mode 100644 include/hw/misc/stm32l4x5_rcc_internals.h create mode 100644 tests/qtest/stm32l4x5_rcc-test.c --=20 2.34.1