From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BD7BC48BC3 for ; Tue, 20 Feb 2024 09:12:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcMAq-0000sb-JA; Tue, 20 Feb 2024 04:12:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAn-0000rT-5y; Tue, 20 Feb 2024 04:12:22 -0500 Received: from mgamail.intel.com ([192.198.163.17]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcMAl-0003Nd-Ay; Tue, 20 Feb 2024 04:12:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708420339; x=1739956339; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sh2QkQ5wss3HOjZ8fhY8YalRgTw6t25jX5kKa/RtD7I=; b=BgM+jP6b0g3VoqDecxvtYsczNbqZ2Ev/g3KHu+9ioOkwlhyVugh6/TjP g9QmMH04g+JICvPWE6Xh0vpzZyzCUoIHlyrToxHNIrl3z9NJOT8AX0DTt ghHFfMBzgC/o3EjodkoJEqLLKav+9tB8+uHIcWygw3vKGDAOQuo+KIloh 4FuYRvl/owqBosg5t7z6VIw2MWxVnf2ZRcztBIav7oVC0wACLGhttSi3h /gitxlMQnR86yhuB2Mgw9cqMFisRfSm185EL4wtOVfyCXV13yJV3tB+Jk triCOQ+dqY31oUgvWlzcLTIvRJROFF9IrqTkON5M99CuOkFEtTUmQLkh5 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="2375017" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="2375017" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 01:12:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="5013057" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa007.jf.intel.com with ESMTP; 20 Feb 2024 01:12:11 -0800 From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC 6/8] i386/cpu: Update cache topology with machine's configuration Date: Tue, 20 Feb 2024 17:25:02 +0800 Message-Id: <20240220092504.726064-7-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220092504.726064-1-zhao1.liu@linux.intel.com> References: <20240220092504.726064-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=192.198.163.17; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.072, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zhao Liu User will configure SMP cache topology via -smp. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d7cb0f1e49b4..4b5c551fe7f0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7582,6 +7582,27 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d; + env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d; + } + + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i; + env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i; + } + + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2; + env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2; + } + + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) { + env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3; + env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { -- 2.34.1