[PATCH v4 0/3] hw/i2c: smbus: Reset fixes

[PATCH v4 0/3] hw/i2c: smbus: Reset fixes

[Joe Komlodi]

Changelog:

v3 -> v4

Patch 1
- Removed the rest of the I3CBus class definition that I forgot to
  remove in v3

v2 -> v3
Patch 1
- Removed I3CBus class definition, since it was unneeded.
- whitespace fixes
- Changed enter_reset to hold_reset

Patch 2
- Moved pointer returned by object_get_canonical_path outside of printf
  so it can be freed

Patch 3
- Changed enter_reset to hold_reset

v1 -> v2
- Dropped 4th patch "hw/i2c: smbus: mux: Reset SMBusDevice state
on reset". After more testing and Corey's comment, I realized it
wasn't needed.

Original message:

Hi all,

This series adds some resets for SMBus and for the I2C core. Along with
it, we make SMBus slave error printing a little more helpful.

These reset issues were very infrequent, they would maybe occur in 1 out
of hundreds of resets in our testing, but the way they happen is pretty
straightforward.

Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.

Thanks,
Joe

Joe Komlodi (3):
  hw/i2c: core: Add reset
  hw/i2c/smbus_slave: Add object path on error prints
  hw/i2c: smbus_slave: Reset state on reset

 hw/i2c/core.c        | 19 +++++++++++++++++++
 hw/i2c/smbus_slave.c | 17 +++++++++++++++--
 2 files changed, 34 insertions(+), 2 deletions(-)

-- 
2.44.0.rc0.258.g7320e95886-goog

[PATCH v4 1/3] hw/i2c: core: Add reset

[Joe Komlodi]

It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.

Signed-off-by: Joe Komlodi <komlodi@google.com>
---
 hw/i2c/core.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 4cf30b2c86..3128067bba 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -23,10 +23,29 @@ static Property i2c_props[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void i2c_bus_hold_reset(Object *obj)
+{
+    I2CBus *bus = I2C_BUS(obj);
+    I2CNode *node, *next;
+
+    bus->broadcast = false;
+    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
+        QLIST_REMOVE(node, next);
+        g_free(node);
+    }
+}
+
+static void i2c_bus_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = i2c_bus_hold_reset;
+}
+
 static const TypeInfo i2c_bus_info = {
     .name = TYPE_I2C_BUS,
     .parent = TYPE_BUS,
     .instance_size = sizeof(I2CBus),
+    .class_init = i2c_bus_class_init,
 };
 
 static int i2c_bus_pre_save(void *opaque)
-- 
2.44.0.rc0.258.g7320e95886-goog

[PATCH v4 2/3] hw/i2c/smbus_slave: Add object path on error prints

[Joe Komlodi]

The current logging doesn't tell us which specific smbus device is an
error state.

Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/smbus_slave.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..9f9afc25a4 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -25,11 +25,15 @@
 #define DPRINTF(fmt, ...) \
 do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
 #define BADF(fmt, ...) \
-do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
+do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
+    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
+            exit(1); } while (0)
 #else
 #define DPRINTF(fmt, ...) do {} while(0)
 #define BADF(fmt, ...) \
-do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__);} while (0)
+do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
+    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
+             } while (0)
 #endif
 
 enum {
-- 
2.44.0.rc0.258.g7320e95886-goog

Re: [PATCH v4 2/3] hw/i2c/smbus_slave: Add object path on error prints

[Philippe Mathieu-Daudé]

On 20/2/24 22:11, Joe Komlodi wrote:
> The current logging doesn't tell us which specific smbus device is an
> error state.
> 
> Signed-off-by: Joe Komlodi <komlodi@google.com>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   hw/i2c/smbus_slave.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
> index 1300c9ec72..9f9afc25a4 100644
> --- a/hw/i2c/smbus_slave.c
> +++ b/hw/i2c/smbus_slave.c
> @@ -25,11 +25,15 @@
>   #define DPRINTF(fmt, ...) \
>   do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
>   #define BADF(fmt, ...) \
> -do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
> +do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
> +    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
> +            exit(1); } while (0)
>   #else
>   #define DPRINTF(fmt, ...) do {} while(0)
>   #define BADF(fmt, ...) \
> -do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__);} while (0)
> +do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
> +    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
> +             } while (0)
>   #endif
>   
>   enum {

Better convert to trace events, so we can enable tracing at runtime.

Anyhow,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

[PATCH v4 3/3] hw/i2c: smbus_slave: Reset state on reset

[Joe Komlodi]

If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.

Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/i2c/smbus_slave.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 9f9afc25a4..4615e8b097 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -201,10 +201,19 @@ static int smbus_i2c_send(I2CSlave *s, uint8_t data)
     return 0;
 }
 
+static void smbus_device_hold_reset(Object *obj)
+{
+    SMBusDevice *dev = SMBUS_DEVICE(obj);
+    dev->mode = SMBUS_IDLE;
+    dev->data_len = 0;
+}
+
 static void smbus_device_class_init(ObjectClass *klass, void *data)
 {
     I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
+    rc->phases.hold = smbus_device_hold_reset;
     sc->event = smbus_i2c_event;
     sc->recv = smbus_i2c_recv;
     sc->send = smbus_i2c_send;
-- 
2.44.0.rc0.258.g7320e95886-goog

Re: [PATCH v4 0/3] hw/i2c: smbus: Reset fixes

[Philippe Mathieu-Daudé]

Hi Joe,

On 20/2/24 22:11, Joe Komlodi wrote:
> Changelog:

> This series adds some resets for SMBus and for the I2C core. Along with
> it, we make SMBus slave error printing a little more helpful.
> 
> These reset issues were very infrequent, they would maybe occur in 1 out
> of hundreds of resets in our testing, but the way they happen is pretty
> straightforward.
> 
> Basically as long as a reset happens in the middle of a transaction, the
> state of the old transaction would still partially be there after the
> reset. Once a new transaction comes in, the partial stale state can
> cause the new transaction to incorrectly fail.

Sorry for jumping late, at v4. I'm a bit confused by this series.

- AFAICT there is no in-band or RESET line with I2C, but
   the AN10216 document mentions:

   I2C Bus recovery

   • Typical case is when masters fails when doing a read
     operation in a slave
   • SDA line is then non usable anymore because of the
     “Slave-Transmitter” mode.
   • Methods to recover the SDA line are:
     – Reset the slave device (assuming the device has a
       Reset pin)
     – Use a bus recovery sequence to leave the “Slave-
       Transmitter” mode
   • Bus recovery sequence is done as following:
     1 - Send 9 clock pulses on SCL line
     2 - Ask the master to keep SDA High until the “Slave-
         Transmitter” releases the SDA line to perform the
         ACK operation
     3 - Keeping SDA High during the ACK means that the
         “Master-Receiver” does not acknowledge the previous
         byte receive
     4 - The “Slave-Transmitter” then goes in an idle state
     5 - The master then sends a STOP command initializing
         completely the bus

- For SMBus Specification Version 2.0:

   3.1.4.2 Power-on reset

   SMBus devices detect a power-on event in one of three ways:
   • By detecting that power is being applied to the device,
   • By an external reset signal that is being asserted or
   • For self-powered or always powered devices, by detecting
     that the SMBus is active (clock and data lines have gone
     high after being low for more than 2 1/2 seconds).

Questions:

- Is the first patch "hw/i2c: core: Add reset" really for
   I2C? Otherwise we could expand smbus form i2cbus, and have
   this reset only for smbus.

- Should we model the "I2C bus recovery sequence" before
   triggering reset?

- Shouldn't we model the smbus 2.5s timeout before triggering
   the reset?

Thanks,

Phil.