From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-ppc@nongnu.org,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Kowshik Jois" <kowsjois@linux.ibm.com>
Subject: [PULL 16/47] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs.
Date: Sat, 24 Feb 2024 01:41:35 +1000 [thread overview]
Message-ID: <20240223154211.1001692-17-npiggin@gmail.com> (raw)
In-Reply-To: <20240223154211.1001692-1-npiggin@gmail.com>
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which can be further
reused as appropriate for correct interpretation.
Suggested-by: Cedric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Kowshik Jois <kowsjois@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_irq.c | 6 ++++--
include/hw/ppc/spapr_irq.h | 14 +++++++++++++-
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index a0d1e1298e..97b2fc42ab 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -23,6 +23,8 @@
#include "trace.h"
+QEMU_BUILD_BUG_ON(SPAPR_IRQ_NR_IPIS > SPAPR_XIRQ_BASE);
+
static const TypeInfo spapr_intc_info = {
.name = TYPE_SPAPR_INTC,
.parent = TYPE_INTERFACE,
@@ -329,7 +331,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
int i;
dev = qdev_new(TYPE_SPAPR_XIVE);
- qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
+ qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_IRQ_NR_IPIS);
/*
* 8 XIVE END structures per CPU. One for each available
* priority
@@ -356,7 +358,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
}
spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr,
- smc->nr_xirqs + SPAPR_XIRQ_BASE);
+ smc->nr_xirqs + SPAPR_IRQ_NR_IPIS);
/*
* Mostly we don't actually need this until reset, except that not
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index c22a72c9e2..4fd2d5853d 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -14,9 +14,21 @@
#include "qom/object.h"
/*
- * IRQ range offsets per device type
+ * The XIVE IRQ backend uses the same layout as the XICS backend but
+ * covers the full range of the IRQ number space. The IRQ numbers for
+ * the CPU IPIs are allocated at the bottom of this space, below 4K,
+ * to preserve compatibility with XICS which does not use that range.
+ */
+
+/*
+ * CPU IPI range (XIVE only)
*/
#define SPAPR_IRQ_IPI 0x0
+#define SPAPR_IRQ_NR_IPIS 0x1000
+
+/*
+ * IRQ range offsets per device type
+ */
#define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
#define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
--
2.42.0
next prev parent reply other threads:[~2024-02-23 16:04 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 15:41 [PULL 00/47] ppc-for-9.0 queue Nicholas Piggin
2024-02-23 15:41 ` [PULL 01/47] target/ppc: Fix lxv/stxv MSR facility check Nicholas Piggin
2024-02-23 15:41 ` [PULL 02/47] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-02-23 15:41 ` [PULL 03/47] tests/avocado: mark boot_linux.py long runtime instead of flaky Nicholas Piggin
2024-02-23 15:41 ` [PULL 04/47] tests/avocado: improve flaky ppc/pnv boot_linux_console.py test Nicholas Piggin
2024-02-23 15:41 ` [PULL 05/47] tests/avocado: ppc add powernv10 boot_linux_console test Nicholas Piggin
2024-02-23 15:41 ` [PULL 06/47] tests/avocado: Add ppc pseries and powernv hash MMU tests Nicholas Piggin
2024-02-23 15:41 ` [PULL 07/47] tests/avocado: Add pseries KVM boot_linux test Nicholas Piggin
2024-02-23 15:41 ` [PULL 08/47] tests/avocado: ppc add hypervisor tests Nicholas Piggin
2024-03-25 11:45 ` Peter Maydell
2024-02-23 15:41 ` [PULL 09/47] tests/avocado: Use default CPU for pseries machine Nicholas Piggin
2024-02-23 15:41 ` [PULL 10/47] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-02-23 15:41 ` [PULL 11/47] target/ppc: Rename registers to match ISA Nicholas Piggin
2024-02-23 15:41 ` [PULL 12/47] hw/ppc/spapr: Add missing license Nicholas Piggin
2024-02-23 15:41 ` [PULL 13/47] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep Nicholas Piggin
2024-02-23 15:41 ` [PULL 14/47] hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr Nicholas Piggin
2024-02-23 15:41 ` [PULL 15/47] hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Nicholas Piggin
2024-02-23 15:41 ` Nicholas Piggin [this message]
2024-02-23 15:41 ` [PULL 17/47] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS Nicholas Piggin
2024-02-23 15:41 ` [PULL 18/47] ppc/spapr: change pseries machine default to POWER10 CPU Nicholas Piggin
2024-02-23 15:41 ` [PULL 19/47] spapr: Tag pseries-2.1 - 2.11 machines as deprecated Nicholas Piggin
2024-02-23 15:41 ` [PULL 20/47] ppc/pnv: Change powernv default to powernv10 Nicholas Piggin
2024-02-23 15:41 ` [PULL 21/47] misc/pca9552: Fix inverted input status Nicholas Piggin
2024-02-23 15:41 ` [PULL 22/47] misc/pca9552: Let external devices set pca9552 inputs Nicholas Piggin
2024-02-23 15:41 ` [PULL 23/47] ppc/pnv: New powernv10-rainier machine type Nicholas Piggin
2024-02-23 15:41 ` [PULL 24/47] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control Nicholas Piggin
2024-02-23 15:41 ` [PULL 25/47] ppc/pnv: Wire up pca9552 GPIO pins " Nicholas Piggin
2024-02-23 15:41 ` [PULL 26/47] ppc/pnv: Use resettable interface to reset child I2C buses Nicholas Piggin
2024-02-23 15:41 ` [PULL 27/47] misc: Add a pca9554 GPIO device model Nicholas Piggin
2024-02-23 15:41 ` [PULL 28/47] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier Nicholas Piggin
2024-02-23 15:41 ` [PULL 29/47] ppc/pnv: Test pnv i2c master and connected devices Nicholas Piggin
2024-02-23 15:41 ` [PULL 30/47] hw/ppc: Add pnv nest pervasive common chiplet model Nicholas Piggin
2024-02-23 15:41 ` [PULL 31/47] hw/ppc: Add N1 " Nicholas Piggin
2024-02-23 15:41 ` [PULL 32/47] hw/ppc: N1 chiplet wiring Nicholas Piggin
2024-02-23 15:41 ` [PULL 33/47] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-02-23 15:41 ` [PULL 34/47] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-02-23 15:41 ` [PULL 35/47] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-02-23 15:41 ` [PULL 36/47] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2024-02-23 15:41 ` [PULL 37/47] ppc/pnv: Add POWER9/10 chiptod model Nicholas Piggin
2024-02-23 15:41 ` [PULL 38/47] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Nicholas Piggin
2024-02-23 15:41 ` [PULL 39/47] ppc/pnv: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-02-23 15:41 ` [PULL 40/47] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-02-23 15:42 ` [PULL 41/47] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-02-23 15:42 ` [PULL 42/47] target/ppc: Fix 440 tlbwe TLB invalidation gaps Nicholas Piggin
2024-02-23 15:42 ` [PULL 43/47] target/ppc: Factor out 4xx ppcemb_tlb_t flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written software TLB entry Nicholas Piggin
2024-02-23 15:42 ` [PULL 45/47] target/ppc: 4xx optimise tlbwe_lo TLB flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 46/47] target/ppc: 440 optimise tlbwe " Nicholas Piggin
2024-02-23 15:42 ` [PULL 47/47] target/ppc: optimise ppcemb_tlb_t flushing Nicholas Piggin
2024-02-24 12:44 ` [PULL 00/47] ppc-for-9.0 queue Peter Maydell
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