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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	qemu-ppc@nongnu.org,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	"Glenn Miles" <milesg@linux.vnet.ibm.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>
Subject: [PULL 21/47] misc/pca9552: Fix inverted input status
Date: Sat, 24 Feb 2024 01:41:40 +1000	[thread overview]
Message-ID: <20240223154211.1001692-22-npiggin@gmail.com> (raw)
In-Reply-To: <20240223154211.1001692-1-npiggin@gmail.com>

From: Glenn Miles <milesg@linux.vnet.ibm.com>

The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins.  A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage scenario.  Existing code was doing the opposite
and setting INPUT0/1 bit to a 1 when the LSn bit was
set to 0, so this commit fixes that.

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/misc/pca9552.c          | 18 +++++++++++++-----
 tests/qtest/pca9552-test.c |  6 +++---
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index 72b653463f..f00a149d61 100644
--- a/hw/misc/pca9552.c
+++ b/hw/misc/pca9552.c
@@ -36,7 +36,10 @@ typedef struct PCA955xClass PCA955xClass;
 
 DECLARE_CLASS_CHECKERS(PCA955xClass, PCA955X,
                        TYPE_PCA955X)
-
+/*
+ * Note:  The LED_ON and LED_OFF configuration values for the PCA955X
+ *        chips are the reverse of the PCA953X family of chips.
+ */
 #define PCA9552_LED_ON   0x0
 #define PCA9552_LED_OFF  0x1
 #define PCA9552_LED_PWM0 0x2
@@ -112,13 +115,18 @@ static void pca955x_update_pin_input(PCA955xState *s)
 
         switch (config) {
         case PCA9552_LED_ON:
-            qemu_set_irq(s->gpio[i], 1);
-            s->regs[input_reg] |= 1 << input_shift;
-            break;
-        case PCA9552_LED_OFF:
+            /* Pin is set to 0V to turn on LED */
             qemu_set_irq(s->gpio[i], 0);
             s->regs[input_reg] &= ~(1 << input_shift);
             break;
+        case PCA9552_LED_OFF:
+            /*
+             * Pin is set to Hi-Z to turn off LED and
+             * pullup sets it to a logical 1.
+             */
+            qemu_set_irq(s->gpio[i], 1);
+            s->regs[input_reg] |= 1 << input_shift;
+            break;
         case PCA9552_LED_PWM0:
         case PCA9552_LED_PWM1:
             /* TODO */
diff --git a/tests/qtest/pca9552-test.c b/tests/qtest/pca9552-test.c
index d80ed93cd3..ccca2b3d91 100644
--- a/tests/qtest/pca9552-test.c
+++ b/tests/qtest/pca9552-test.c
@@ -60,7 +60,7 @@ static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc)
     g_assert_cmphex(value, ==, 0x55);
 
     value = i2c_get8(i2cdev, PCA9552_INPUT0);
-    g_assert_cmphex(value, ==, 0x0);
+    g_assert_cmphex(value, ==, 0xFF);
 
     pca9552_init(i2cdev);
 
@@ -68,13 +68,13 @@ static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc)
     g_assert_cmphex(value, ==, 0x54);
 
     value = i2c_get8(i2cdev, PCA9552_INPUT0);
-    g_assert_cmphex(value, ==, 0x01);
+    g_assert_cmphex(value, ==, 0xFE);
 
     value = i2c_get8(i2cdev, PCA9552_LS3);
     g_assert_cmphex(value, ==, 0x54);
 
     value = i2c_get8(i2cdev, PCA9552_INPUT1);
-    g_assert_cmphex(value, ==, 0x10);
+    g_assert_cmphex(value, ==, 0xEF);
 }
 
 static void pca9552_register_nodes(void)
-- 
2.42.0



  parent reply	other threads:[~2024-02-23 16:01 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-23 15:41 [PULL 00/47] ppc-for-9.0 queue Nicholas Piggin
2024-02-23 15:41 ` [PULL 01/47] target/ppc: Fix lxv/stxv MSR facility check Nicholas Piggin
2024-02-23 15:41 ` [PULL 02/47] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-02-23 15:41 ` [PULL 03/47] tests/avocado: mark boot_linux.py long runtime instead of flaky Nicholas Piggin
2024-02-23 15:41 ` [PULL 04/47] tests/avocado: improve flaky ppc/pnv boot_linux_console.py test Nicholas Piggin
2024-02-23 15:41 ` [PULL 05/47] tests/avocado: ppc add powernv10 boot_linux_console test Nicholas Piggin
2024-02-23 15:41 ` [PULL 06/47] tests/avocado: Add ppc pseries and powernv hash MMU tests Nicholas Piggin
2024-02-23 15:41 ` [PULL 07/47] tests/avocado: Add pseries KVM boot_linux test Nicholas Piggin
2024-02-23 15:41 ` [PULL 08/47] tests/avocado: ppc add hypervisor tests Nicholas Piggin
2024-03-25 11:45   ` Peter Maydell
2024-02-23 15:41 ` [PULL 09/47] tests/avocado: Use default CPU for pseries machine Nicholas Piggin
2024-02-23 15:41 ` [PULL 10/47] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-02-23 15:41 ` [PULL 11/47] target/ppc: Rename registers to match ISA Nicholas Piggin
2024-02-23 15:41 ` [PULL 12/47] hw/ppc/spapr: Add missing license Nicholas Piggin
2024-02-23 15:41 ` [PULL 13/47] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep Nicholas Piggin
2024-02-23 15:41 ` [PULL 14/47] hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr Nicholas Piggin
2024-02-23 15:41 ` [PULL 15/47] hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Nicholas Piggin
2024-02-23 15:41 ` [PULL 16/47] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs Nicholas Piggin
2024-02-23 15:41 ` [PULL 17/47] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS Nicholas Piggin
2024-02-23 15:41 ` [PULL 18/47] ppc/spapr: change pseries machine default to POWER10 CPU Nicholas Piggin
2024-02-23 15:41 ` [PULL 19/47] spapr: Tag pseries-2.1 - 2.11 machines as deprecated Nicholas Piggin
2024-02-23 15:41 ` [PULL 20/47] ppc/pnv: Change powernv default to powernv10 Nicholas Piggin
2024-02-23 15:41 ` Nicholas Piggin [this message]
2024-02-23 15:41 ` [PULL 22/47] misc/pca9552: Let external devices set pca9552 inputs Nicholas Piggin
2024-02-23 15:41 ` [PULL 23/47] ppc/pnv: New powernv10-rainier machine type Nicholas Piggin
2024-02-23 15:41 ` [PULL 24/47] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control Nicholas Piggin
2024-02-23 15:41 ` [PULL 25/47] ppc/pnv: Wire up pca9552 GPIO pins " Nicholas Piggin
2024-02-23 15:41 ` [PULL 26/47] ppc/pnv: Use resettable interface to reset child I2C buses Nicholas Piggin
2024-02-23 15:41 ` [PULL 27/47] misc: Add a pca9554 GPIO device model Nicholas Piggin
2024-02-23 15:41 ` [PULL 28/47] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier Nicholas Piggin
2024-02-23 15:41 ` [PULL 29/47] ppc/pnv: Test pnv i2c master and connected devices Nicholas Piggin
2024-02-23 15:41 ` [PULL 30/47] hw/ppc: Add pnv nest pervasive common chiplet model Nicholas Piggin
2024-02-23 15:41 ` [PULL 31/47] hw/ppc: Add N1 " Nicholas Piggin
2024-02-23 15:41 ` [PULL 32/47] hw/ppc: N1 chiplet wiring Nicholas Piggin
2024-02-23 15:41 ` [PULL 33/47] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-02-23 15:41 ` [PULL 34/47] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-02-23 15:41 ` [PULL 35/47] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-02-23 15:41 ` [PULL 36/47] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2024-02-23 15:41 ` [PULL 37/47] ppc/pnv: Add POWER9/10 chiptod model Nicholas Piggin
2024-02-23 15:41 ` [PULL 38/47] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Nicholas Piggin
2024-02-23 15:41 ` [PULL 39/47] ppc/pnv: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-02-23 15:41 ` [PULL 40/47] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-02-23 15:42 ` [PULL 41/47] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-02-23 15:42 ` [PULL 42/47] target/ppc: Fix 440 tlbwe TLB invalidation gaps Nicholas Piggin
2024-02-23 15:42 ` [PULL 43/47] target/ppc: Factor out 4xx ppcemb_tlb_t flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written software TLB entry Nicholas Piggin
2024-02-23 15:42 ` [PULL 45/47] target/ppc: 4xx optimise tlbwe_lo TLB flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 46/47] target/ppc: 440 optimise tlbwe " Nicholas Piggin
2024-02-23 15:42 ` [PULL 47/47] target/ppc: optimise ppcemb_tlb_t flushing Nicholas Piggin
2024-02-24 12:44 ` [PULL 00/47] ppc-for-9.0 queue Peter Maydell

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