qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	qemu-ppc@nongnu.org,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Subject: [PULL 36/47] target/ppc: Fix move-to timebase SPR access permissions
Date: Sat, 24 Feb 2024 01:41:55 +1000	[thread overview]
Message-ID: <20240223154211.1001692-37-npiggin@gmail.com> (raw)
In-Reply-To: <20240223154211.1001692-1-npiggin@gmail.com>

The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/helper_regs.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 94c9a5a5c1..410b39c231 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -468,18 +468,33 @@ void register_generic_sprs(PowerPCCPU *cpu)
                  &spr_read_tbl, SPR_NOACCESS,
                  &spr_read_tbl, SPR_NOACCESS,
                  0x00000000);
-    spr_register(env, SPR_WR_TBL, "TBL",
-                 &spr_read_tbl, SPR_NOACCESS,
-                 &spr_read_tbl, &spr_write_tbl,
-                 0x00000000);
     spr_register(env, SPR_TBU, "TBU",
                  &spr_read_tbu, SPR_NOACCESS,
                  &spr_read_tbu, SPR_NOACCESS,
                  0x00000000);
-    spr_register(env, SPR_WR_TBU, "TBU",
-                 &spr_read_tbu, SPR_NOACCESS,
-                 &spr_read_tbu, &spr_write_tbu,
-                 0x00000000);
+#ifndef CONFIG_USER_ONLY
+    if (env->has_hv_mode) {
+        spr_register_hv(env, SPR_WR_TBL, "TBL",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, &spr_write_tbl,
+                        0x00000000);
+        spr_register_hv(env, SPR_WR_TBU, "TBU",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, &spr_write_tbu,
+                        0x00000000);
+    } else {
+        spr_register(env, SPR_WR_TBL, "TBL",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     SPR_NOACCESS, &spr_write_tbl,
+                     0x00000000);
+        spr_register(env, SPR_WR_TBU, "TBU",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     SPR_NOACCESS, &spr_write_tbu,
+                     0x00000000);
+    }
+#endif
 }
 
 void register_non_embedded_sprs(CPUPPCState *env)
-- 
2.42.0



  parent reply	other threads:[~2024-02-23 16:04 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-23 15:41 [PULL 00/47] ppc-for-9.0 queue Nicholas Piggin
2024-02-23 15:41 ` [PULL 01/47] target/ppc: Fix lxv/stxv MSR facility check Nicholas Piggin
2024-02-23 15:41 ` [PULL 02/47] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-02-23 15:41 ` [PULL 03/47] tests/avocado: mark boot_linux.py long runtime instead of flaky Nicholas Piggin
2024-02-23 15:41 ` [PULL 04/47] tests/avocado: improve flaky ppc/pnv boot_linux_console.py test Nicholas Piggin
2024-02-23 15:41 ` [PULL 05/47] tests/avocado: ppc add powernv10 boot_linux_console test Nicholas Piggin
2024-02-23 15:41 ` [PULL 06/47] tests/avocado: Add ppc pseries and powernv hash MMU tests Nicholas Piggin
2024-02-23 15:41 ` [PULL 07/47] tests/avocado: Add pseries KVM boot_linux test Nicholas Piggin
2024-02-23 15:41 ` [PULL 08/47] tests/avocado: ppc add hypervisor tests Nicholas Piggin
2024-03-25 11:45   ` Peter Maydell
2024-02-23 15:41 ` [PULL 09/47] tests/avocado: Use default CPU for pseries machine Nicholas Piggin
2024-02-23 15:41 ` [PULL 10/47] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-02-23 15:41 ` [PULL 11/47] target/ppc: Rename registers to match ISA Nicholas Piggin
2024-02-23 15:41 ` [PULL 12/47] hw/ppc/spapr: Add missing license Nicholas Piggin
2024-02-23 15:41 ` [PULL 13/47] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep Nicholas Piggin
2024-02-23 15:41 ` [PULL 14/47] hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr Nicholas Piggin
2024-02-23 15:41 ` [PULL 15/47] hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Nicholas Piggin
2024-02-23 15:41 ` [PULL 16/47] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs Nicholas Piggin
2024-02-23 15:41 ` [PULL 17/47] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS Nicholas Piggin
2024-02-23 15:41 ` [PULL 18/47] ppc/spapr: change pseries machine default to POWER10 CPU Nicholas Piggin
2024-02-23 15:41 ` [PULL 19/47] spapr: Tag pseries-2.1 - 2.11 machines as deprecated Nicholas Piggin
2024-02-23 15:41 ` [PULL 20/47] ppc/pnv: Change powernv default to powernv10 Nicholas Piggin
2024-02-23 15:41 ` [PULL 21/47] misc/pca9552: Fix inverted input status Nicholas Piggin
2024-02-23 15:41 ` [PULL 22/47] misc/pca9552: Let external devices set pca9552 inputs Nicholas Piggin
2024-02-23 15:41 ` [PULL 23/47] ppc/pnv: New powernv10-rainier machine type Nicholas Piggin
2024-02-23 15:41 ` [PULL 24/47] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control Nicholas Piggin
2024-02-23 15:41 ` [PULL 25/47] ppc/pnv: Wire up pca9552 GPIO pins " Nicholas Piggin
2024-02-23 15:41 ` [PULL 26/47] ppc/pnv: Use resettable interface to reset child I2C buses Nicholas Piggin
2024-02-23 15:41 ` [PULL 27/47] misc: Add a pca9554 GPIO device model Nicholas Piggin
2024-02-23 15:41 ` [PULL 28/47] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier Nicholas Piggin
2024-02-23 15:41 ` [PULL 29/47] ppc/pnv: Test pnv i2c master and connected devices Nicholas Piggin
2024-02-23 15:41 ` [PULL 30/47] hw/ppc: Add pnv nest pervasive common chiplet model Nicholas Piggin
2024-02-23 15:41 ` [PULL 31/47] hw/ppc: Add N1 " Nicholas Piggin
2024-02-23 15:41 ` [PULL 32/47] hw/ppc: N1 chiplet wiring Nicholas Piggin
2024-02-23 15:41 ` [PULL 33/47] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-02-23 15:41 ` [PULL 34/47] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-02-23 15:41 ` [PULL 35/47] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-02-23 15:41 ` Nicholas Piggin [this message]
2024-02-23 15:41 ` [PULL 37/47] ppc/pnv: Add POWER9/10 chiptod model Nicholas Piggin
2024-02-23 15:41 ` [PULL 38/47] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines Nicholas Piggin
2024-02-23 15:41 ` [PULL 39/47] ppc/pnv: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-02-23 15:41 ` [PULL 40/47] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-02-23 15:42 ` [PULL 41/47] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-02-23 15:42 ` [PULL 42/47] target/ppc: Fix 440 tlbwe TLB invalidation gaps Nicholas Piggin
2024-02-23 15:42 ` [PULL 43/47] target/ppc: Factor out 4xx ppcemb_tlb_t flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written software TLB entry Nicholas Piggin
2024-02-23 15:42 ` [PULL 45/47] target/ppc: 4xx optimise tlbwe_lo TLB flushing Nicholas Piggin
2024-02-23 15:42 ` [PULL 46/47] target/ppc: 440 optimise tlbwe " Nicholas Piggin
2024-02-23 15:42 ` [PULL 47/47] target/ppc: optimise ppcemb_tlb_t flushing Nicholas Piggin
2024-02-24 12:44 ` [PULL 00/47] ppc-for-9.0 queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240223154211.1001692-37-npiggin@gmail.com \
    --to=npiggin@gmail.com \
    --cc=clg@kaod.org \
    --cc=danielhb413@gmail.com \
    --cc=harshpb@linux.ibm.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).