* [PATCH v2] target/riscv: Fix shift count overflow
@ 2024-02-25 3:27 demin.han
2024-02-25 10:16 ` Daniel Henrique Barboza
2024-02-25 16:49 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 3+ messages in thread
From: demin.han @ 2024-02-25 3:27 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, dbarboza, alistair.francis
The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
target/riscv/vector_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb2..fe56c007d5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
target_ulong reserved = s2 &
MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+ uint16_t vlen = cpu->cfg.vlenb << 3;
int8_t lmul;
if (vlmul & 4) {
@@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
- * vlenb >> (8 - 3 - lmul) >= sew
*/
- if (vlmul == 4 ||
- cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+ if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
vill = true;
}
}
--
2.43.2
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] target/riscv: Fix shift count overflow
2024-02-25 3:27 [PATCH v2] target/riscv: Fix shift count overflow demin.han
@ 2024-02-25 10:16 ` Daniel Henrique Barboza
2024-02-25 16:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-25 10:16 UTC (permalink / raw)
To: demin.han, qemu-devel; +Cc: qemu-riscv, alistair.francis
On 2/25/24 00:27, demin.han wrote:
> The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
> and results in wrong vill.
>
> Signed-off-by: demin.han <demin.han@starfivetech.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/vector_helper.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 84cec73eb2..fe56c007d5 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> target_ulong reserved = s2 &
> MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> + uint16_t vlen = cpu->cfg.vlenb << 3;
> int8_t lmul;
>
> if (vlmul & 4) {
> @@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> * VLEN * LMUL >= SEW
> * VLEN >> (8 - lmul) >= sew
> * (vlenb << 3) >> (8 - lmul) >= sew
> - * vlenb >> (8 - 3 - lmul) >= sew
> */
> - if (vlmul == 4 ||
> - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> + if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> vill = true;
> }
> }
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] target/riscv: Fix shift count overflow
2024-02-25 3:27 [PATCH v2] target/riscv: Fix shift count overflow demin.han
2024-02-25 10:16 ` Daniel Henrique Barboza
@ 2024-02-25 16:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-02-25 16:49 UTC (permalink / raw)
To: demin.han, qemu-devel; +Cc: qemu-riscv, dbarboza, alistair.francis
On 25/2/24 04:27, demin.han wrote:
> The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
Typo "negative".
> and results in wrong vill.
>
> Signed-off-by: demin.han <demin.han@starfivetech.com>
> ---
> target/riscv/vector_helper.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 84cec73eb2..fe56c007d5 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -44,6 +44,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> target_ulong reserved = s2 &
> MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> + uint16_t vlen = cpu->cfg.vlenb << 3;
> int8_t lmul;
>
> if (vlmul & 4) {
> @@ -53,10 +54,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> * VLEN * LMUL >= SEW
> * VLEN >> (8 - lmul) >= sew
> * (vlenb << 3) >> (8 - lmul) >= sew
> - * vlenb >> (8 - 3 - lmul) >= sew
> */
> - if (vlmul == 4 ||
> - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> + if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
> vill = true;
> }
> }
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-02-25 3:27 [PATCH v2] target/riscv: Fix shift count overflow demin.han
2024-02-25 10:16 ` Daniel Henrique Barboza
2024-02-25 16:49 ` Philippe Mathieu-Daudé
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