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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Thomas Huth" <thuth@redhat.com>,
	"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
	"Anton Johansson" <anjo@rev.ng>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Zhao Liu" <zhao1.liu@intel.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Ani Sinha" <anisinha@redhat.com>,
	"Bernhard Beschow" <shentey@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Laszlo Ersek" <lersek@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 2/5] hw/i386/piix: Set CPU SMI# interrupt using QDev GPIO API
Date: Mon, 26 Feb 2024 17:49:09 +0100	[thread overview]
Message-ID: <20240226164913.94077-3-philmd@linaro.org> (raw)
In-Reply-To: <20240226164913.94077-1-philmd@linaro.org>

Use the CPU "SMI" IRQ, removing a call to cpu_interrupt()
from hw/.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/i386/pc.h | 2 --
 hw/i386/pc.c         | 9 ---------
 hw/i386/pc_piix.c    | 4 ++--
 3 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 4bb1899602..c8227e18c3 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -148,8 +148,6 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
 /* pc.c */
 extern int fd_bootchk;
 
-void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
-
 #define PCI_HOST_PROP_RAM_MEM          "ram-mem"
 #define PCI_HOST_PROP_PCI_MEM          "pci-mem"
 #define PCI_HOST_PROP_SYSTEM_MEM       "system-mem"
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 880e95de26..1df9f5ba90 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -651,15 +651,6 @@ static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
     return true;
 }
 
-void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
-{
-    X86CPU *cpu = opaque;
-
-    if (level) {
-        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
-    }
-}
-
 static
 void pc_machine_done(Notifier *notifier, void *data)
 {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ce6aad758d..447130ade1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -345,9 +345,9 @@ static void pc_init1(MachineState *machine,
     pc_cmos_init(pcms, x86ms->rtc);
 
     if (piix4_pm) {
-        smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
-
+        smi_irq = qdev_get_gpio_in_named(DEVICE(first_cpu), "SMI", 0);
         qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
+
         pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
         /* TODO: Populate SPD eeprom data.  */
         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
-- 
2.41.0



  parent reply	other threads:[~2024-02-26 16:49 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-26 16:49 [RFC PATCH 0/5] hw/i386/q35: Decouple virtual SMI# lines and wire them to ICH9 chipset Philippe Mathieu-Daudé
2024-02-26 16:49 ` [PATCH 1/5] target/i386/cpu: Expose SMI# IRQ line via QDev Philippe Mathieu-Daudé
2024-02-26 16:49 ` Philippe Mathieu-Daudé [this message]
2024-02-26 16:49 ` [RFC PATCH 3/5] hw/ahci/ich9_tco: Set CPU SMI# interrupt using QDev GPIO API Philippe Mathieu-Daudé
2024-02-26 16:49 ` [RFC PATCH 4/5] hw/i386/q35: Wire virtual SMI# lines to ICH9 chipset Philippe Mathieu-Daudé
2024-02-28 16:43   ` Zhao Liu
2024-03-07 19:43     ` Thomas Huth
2024-03-08  8:08       ` Philippe Mathieu-Daudé
2024-03-08  8:10         ` Laszlo Ersek
2024-03-08  8:53           ` Bernhard Beschow
2024-03-08 16:06         ` Thomas Huth
2024-03-08 16:12           ` Peter Maydell
2024-03-08 16:41           ` Philippe Mathieu-Daudé
2024-02-26 16:49 ` [RFC PATCH 5/5] hw/isa: Build ich9_lpc.c once Philippe Mathieu-Daudé
2024-02-28  3:06 ` [RFC PATCH 0/5] hw/i386/q35: Decouple virtual SMI# lines and wire them to ICH9 chipset Laszlo Ersek

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