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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v3 2/6] exec/memattrs: Remove target_tlb_bit*
Date: Fri,  1 Mar 2024 10:41:06 -1000	[thread overview]
Message-ID: <20240301204110.656742-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org>

These fields are no longer used since 937f224559.
Target specific extensions to the page tables should be done
with TARGET_PAGE_ENTRY_EXTRA.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/memattrs.h | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d04170aa27..afa885f983 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -54,16 +54,6 @@ typedef struct MemTxAttrs {
     unsigned int requester_id:16;
     /* Invert endianness for this page */
     unsigned int byte_swap:1;
-    /*
-     * The following are target-specific page-table bits.  These are not
-     * related to actual memory transactions at all.  However, this structure
-     * is part of the tlb_fill interface, cached in the cputlb structure,
-     * and has unused bits.  These fields will be read by target-specific
-     * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
-     */
-    unsigned int target_tlb_bit0 : 1;
-    unsigned int target_tlb_bit1 : 1;
-    unsigned int target_tlb_bit2 : 1;
 } MemTxAttrs;
 
 /* Bus masters which don't specify any attributes will get this,
-- 
2.34.1



  parent reply	other threads:[~2024-03-01 20:42 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-01 20:41 [PATCH v3 0/6] target/arm: Do memory alignment check for device memory Richard Henderson
2024-03-01 20:41 ` [PATCH v3 1/6] target/arm: Support 32-byte alignment in pow2_align Richard Henderson
2024-03-01 20:41 ` Richard Henderson [this message]
2024-03-01 20:41 ` [PATCH v3 3/6] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Richard Henderson
2024-03-01 20:41 ` [PATCH v3 4/6] accel/tcg: Add TLB_CHECK_ALIGNED Richard Henderson
2024-03-01 20:41 ` [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled Richard Henderson
2024-04-16 15:11   ` Jonathan Cameron via
2024-04-17 20:07     ` Richard Henderson
2024-04-18  8:15       ` Jonathan Cameron via
2024-04-18 17:40         ` Jonathan Cameron via
2024-04-19 11:52           ` [edk2-devel] " Gerd Hoffmann
2024-04-19 16:09             ` Jonathan Cameron via
2024-04-19 16:36               ` Ard Biesheuvel
2024-04-19 17:38                 ` Ard Biesheuvel
2024-04-22 15:26   ` Clément Chigot
2024-04-22 15:47     ` Richard Henderson
2024-04-22 15:59       ` Peter Maydell
2024-03-01 20:41 ` [PATCH v3 6/6] target/arm: Do memory type alignment check when translation enabled Richard Henderson
2024-03-04 17:10   ` Peter Maydell
2024-03-04 17:27     ` Richard Henderson
2024-03-04 17:12 ` [PATCH v3 0/6] target/arm: Do memory alignment check for device memory Peter Maydell

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