From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 02/41] target/sparc: Fix FEXPAND
Date: Fri, 1 Mar 2024 19:15:22 -1000 [thread overview]
Message-ID: <20240302051601.53649-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org>
This is a 2-operand instruction, not 3-operand.
Worse, we took the source from the wrong operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/helper.h | 2 +-
target/sparc/translate.c | 20 +++++++++++++++++++-
target/sparc/vis_helper.c | 6 +++---
target/sparc/insns.decode | 2 +-
4 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index e55fad5b8c..ef21ef49ef 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_1(fexpand, TCG_CALL_NO_RWG_SE, i64, i32)
DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 692ce0b010..5016664869 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4314,6 +4314,25 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd)
TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod)
TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox)
+static bool do_df(DisasContext *dc, arg_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i32))
+{
+ TCGv_i64 dst;
+ TCGv_i32 src;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = tcg_temp_new_i64();
+ src = gen_load_fpr_F(dc, a->rs);
+ func(dst, src);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(FEXPAND, VIS1, do_df, a, gen_helper_fexpand)
+
static bool do_env_df(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i32))
{
@@ -4545,7 +4564,6 @@ TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16)
TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16)
TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16)
TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge)
-TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand)
TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64)
TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64)
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 7763b16c24..db2e6dd6c1 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -260,13 +260,13 @@ uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2)
return d.ll;
}
-uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
+uint64_t helper_fexpand(uint32_t src2)
{
VIS32 s;
VIS64 d;
- s.l = (uint32_t)src1;
- d.ll = src2;
+ s.l = src2;
+ d.ll = 0;
d.VIS_W64(0) = s.VIS_B32(0) << 4;
d.VIS_W64(1) = s.VIS_B32(1) << 4;
d.VIS_W64(2) = s.VIS_B32(2) << 4;
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 2d26404cb2..e2d8a07dc4 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -352,7 +352,7 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r
- FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r
+ FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @r_r2
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
--
2.34.1
next prev parent reply other threads:[~2024-03-02 5:18 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-02 5:15 [PATCH 00/41] target/sparc: Implement VIS4 Richard Henderson
2024-03-02 5:15 ` [PATCH 01/41] linux-user/sparc: Add more hwcap bits for sparc64 Richard Henderson
2024-03-02 5:15 ` Richard Henderson [this message]
2024-03-02 5:15 ` [PATCH 03/41] target/sparc: Fix FMUL8x16 Richard Henderson
2024-03-02 5:15 ` [PATCH 04/41] target/sparc: Fix FMUL8x16A{U,L} Richard Henderson
2024-04-30 8:07 ` Mark Cave-Ayland
2024-03-02 5:15 ` [PATCH 05/41] target/sparc: Fix FMULD8*X16 Richard Henderson
2024-03-02 5:15 ` [PATCH 06/41] target/sparc: Fix FPMERGE Richard Henderson
2024-03-02 5:15 ` [PATCH 07/41] target/sparc: Split out do_ms16b Richard Henderson
2024-03-02 5:15 ` [PATCH 08/41] target/sparc: Perform DFPREG/QFPREG in decodetree Richard Henderson
2024-05-10 15:18 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 09/41] target/sparc: Remove gen_dest_fpr_D Richard Henderson
2024-05-10 15:18 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 10/41] target/sparc: Remove cpu_fpr[] Richard Henderson
2024-03-02 5:15 ` [PATCH 11/41] target/sparc: Use gvec for VIS1 parallel add/sub Richard Henderson
2024-05-10 15:21 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 12/41] target/sparc: Implement FMAf extension Richard Henderson
2024-03-02 5:15 ` [PATCH 13/41] target/sparc: Add feature bits for VIS 3 Richard Henderson
2024-05-10 17:05 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 14/41] target/sparc: Implement ADDXC, ADDXCcc Richard Henderson
2024-05-10 16:16 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 15/41] target/sparc: Implement CMASK instructions Richard Henderson
2024-03-02 5:15 ` [PATCH 16/41] target/sparc: Implement FCHKSM16 Richard Henderson
2024-03-02 5:15 ` [PATCH 17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD Richard Henderson
2024-03-02 5:15 ` [PATCH 18/41] target/sparc: Implement FNMUL Richard Henderson
2024-03-02 5:15 ` [PATCH 19/41] target/sparc: Implement FLCMP Richard Henderson
2024-03-02 5:15 ` [PATCH 20/41] target/sparc: Implement FMEAN16 Richard Henderson
2024-03-02 5:15 ` [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64 Richard Henderson
2024-05-10 16:19 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 22/41] target/sparc: Implement FPADDS, FPSUBS Richard Henderson
2024-03-02 5:15 ` [PATCH 23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 Richard Henderson
2024-03-02 5:15 ` [PATCH 24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS Richard Henderson
2024-03-02 5:15 ` [PATCH 25/41] target/sparc: Implement LDXEFSR Richard Henderson
2024-03-02 5:15 ` [PATCH 26/41] target/sparc: Implement LZCNT Richard Henderson
2024-05-10 17:22 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd Richard Henderson
2024-03-02 5:15 ` [PATCH 28/41] target/sparc: Implement PDISTN Richard Henderson
2024-05-10 17:28 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 29/41] target/sparc: Implement UMULXHI Richard Henderson
2024-03-02 5:15 ` [PATCH 30/41] target/sparc: Implement XMULX Richard Henderson
2024-03-02 5:15 ` [PATCH 31/41] target/sparc: Enable VIS3 feature bit Richard Henderson
2024-03-02 5:15 ` [PATCH 32/41] target/sparc: Implement IMA extension Richard Henderson
2024-05-10 17:09 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 33/41] target/sparc: Add feature bit for VIS4 Richard Henderson
2024-05-10 17:05 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 34/41] target/sparc: Implement FALIGNDATAi Richard Henderson
2024-03-02 5:15 ` [PATCH 35/41] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS Richard Henderson
2024-05-10 16:20 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 36/41] target/sparc: Implement VIS4 comparisons Richard Henderson
2024-03-02 5:15 ` [PATCH 37/41] target/sparc: Implement FPMIN, FPMAX Richard Henderson
2024-05-10 17:11 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 38/41] target/sparc: Implement SUBXC, SUBXCcc Richard Henderson
2024-05-10 16:21 ` Philippe Mathieu-Daudé
2024-03-02 5:15 ` [PATCH 39/41] target/sparc: Implement MWAIT Richard Henderson
2024-03-02 5:16 ` [PATCH 40/41] target/sparc: Implement monitor asis Richard Henderson
2024-05-10 17:04 ` Philippe Mathieu-Daudé
2024-03-02 5:16 ` [PATCH 41/41] target/sparc: Enable VIS4 feature bit Richard Henderson
2024-05-10 17:16 ` Philippe Mathieu-Daudé
2024-05-10 17:31 ` Philippe Mathieu-Daudé
2024-03-05 10:20 ` [PATCH 00/41] target/sparc: Implement VIS4 Mark Cave-Ayland
2024-04-29 20:52 ` Mark Cave-Ayland
2024-04-29 21:02 ` Richard Henderson
2024-04-29 21:10 ` Mark Cave-Ayland
2024-05-15 15:30 ` Richard Henderson
2024-05-16 20:36 ` Mark Cave-Ayland
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