From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0
Date: Fri, 8 Mar 2024 15:50:03 +0000 [thread overview]
Message-ID: <20240308155015.3637663-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20240308155015.3637663-1-peter.maydell@linaro.org>
The timer _EL02 registers should UNDEF for invalid accesses from EL2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
delivering the exception to EL2 with the wrong syndrome.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 90c4fb72ce4..978df6f2823 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6551,7 +6551,7 @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return CP_ACCESS_OK;
}
--
2.34.1
next prev parent reply other threads:[~2024-03-08 15:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-08 15:50 [PULL 00/14] target-arm queue Peter Maydell
2024-03-08 15:50 ` [PULL 01/14] target/arm: Move some register related defines to internals.h Peter Maydell
2024-03-08 15:50 ` Peter Maydell [this message]
2024-03-08 15:50 ` [PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions Peter Maydell
2024-03-08 15:50 ` [PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written Peter Maydell
2024-03-08 15:50 ` [PULL 05/14] target/arm: Implement new FEAT_ECV trap bits Peter Maydell
2024-03-08 15:50 ` [PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 Peter Maydell
2024-03-08 15:50 ` [PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling Peter Maydell
2024-03-08 15:50 ` [PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU Peter Maydell
2024-03-08 15:50 ` [PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO Peter Maydell
2024-03-08 15:50 ` [PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC Peter Maydell
2024-03-08 15:50 ` [PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase Peter Maydell
2024-03-08 15:50 ` [PULL 12/14] target/arm: Fix 32-bit SMOPA Peter Maydell
2024-03-08 15:50 ` [PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later Peter Maydell
2024-03-08 15:50 ` [PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file Peter Maydell
2024-03-09 14:58 ` [PULL 00/14] target-arm queue Peter Maydell
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