From: Klaus Jensen <its@irrelevant.dk>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-block@nongnu.org, "Klaus Jensen" <its@irrelevant.dk>,
"Jesper Devantier" <foss@defmacro.it>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Keith Busch" <kbusch@kernel.org>,
"Klaus Jensen" <k.jensen@samsung.com>,
qemu-stable@nongnu.org
Subject: [PULL 5/6] hw/nvme: generalize the mbar size helper
Date: Mon, 11 Mar 2024 20:11:11 +0100 [thread overview]
Message-ID: <20240311191105.35224-13-its@irrelevant.dk> (raw)
In-Reply-To: <20240311191105.35224-8-its@irrelevant.dk>
From: Klaus Jensen <k.jensen@samsung.com>
Generalize the mbar size helper such that it can handle cases where the
MSI-X table and PBA are expected to be in an exclusive bar.
Cc: qemu-stable@nongnu.org
Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/nvme/ctrl.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 6c5a2b875da8..5ee8deda22a4 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8015,13 +8015,18 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
memory_region_set_enabled(&n->pmr.dev->mr, false);
}
-static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
- unsigned *msix_table_offset,
- unsigned *msix_pba_offset)
+static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs,
+ unsigned *msix_table_offset,
+ unsigned *msix_pba_offset)
{
- uint64_t bar_size, msix_table_size, msix_pba_size;
+ uint64_t bar_size, msix_table_size;
bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE;
+
+ if (total_irqs == 0) {
+ goto out;
+ }
+
bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
if (msix_table_offset) {
@@ -8036,11 +8041,10 @@ static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
*msix_pba_offset = bar_size;
}
- msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8;
- bar_size += msix_pba_size;
+ bar_size += QEMU_ALIGN_UP(total_irqs, 64) / 8;
- bar_size = pow2ceil(bar_size);
- return bar_size;
+out:
+ return pow2ceil(bar_size);
}
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
@@ -8048,7 +8052,7 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
uint16_t vf_dev_id = n->params.use_intel_id ?
PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
NvmePriCtrlCap *cap = &n->pri_ctrl_cap;
- uint64_t bar_size = nvme_bar_size(le16_to_cpu(cap->vqfrsm),
+ uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm),
NULL, NULL);
@@ -8110,8 +8114,8 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
}
/* add one to max_ioqpairs to account for the admin queue pair */
- bar_size = nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize,
- &msix_table_offset, &msix_pba_offset);
+ bar_size = nvme_mbar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize,
+ &msix_table_offset, &msix_pba_offset);
memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
--
2.44.0
next prev parent reply other threads:[~2024-03-11 19:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-11 19:11 [PULL 0/6] hw/nvme updates Klaus Jensen
2024-03-11 19:11 ` [PULL 1/6] hw/nvme: separate 'serial' property for VFs Klaus Jensen
2024-03-11 19:11 ` [PULL 2/6] hw/nvme: fix invalid check on mcl Klaus Jensen
2024-03-11 19:11 ` [PULL 3/6] MAINTAINERS: add Jesper as reviewer on hw/nvme Klaus Jensen
2024-03-11 19:11 ` [PULL 4/6] hw/nvme: Add NVMe NGUID property Klaus Jensen
2024-03-11 19:11 ` Klaus Jensen [this message]
2024-03-11 19:11 ` [PULL 6/6] hw/nvme: add machine compatibility parameter to enable msix exclusive bar Klaus Jensen
2024-03-12 11:34 ` [PULL 0/6] hw/nvme updates Peter Maydell
2024-03-12 11:59 ` Klaus Jensen
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