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Iglesias" , Laurent Vivier , Anton Johansson , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.1 5/8] target/microblaze: Restrict 64-bit 'res_addr' to system emulation Date: Tue, 19 Mar 2024 07:28:52 +0100 Message-ID: <20240319062855.8025-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240319062855.8025-1-philmd@linaro.org> References: <20240319062855.8025-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'res_addr' is only used in system emulation, where we have TARGET_LONG_BITS = 64, so we can directly use the native uint64_t type instead of target_ulong. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 10 +++++----- target/microblaze/cpu.c | 2 ++ target/microblaze/machine.c | 2 +- target/microblaze/translate.c | 9 +++++++-- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c0c7574dbd..c3e2aba0ec 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -260,11 +260,6 @@ struct CPUArchState { /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; - /* lwx/swx reserved address */ -#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ - target_ulong res_addr; - uint32_t res_val; - /* Internal flags. */ #define IMM_FLAG (1 << 0) #define BIMM_FLAG (1 << 1) @@ -286,6 +281,11 @@ struct CPUArchState { uint32_t iflags; #if !defined(CONFIG_USER_ONLY) + /* lwx/swx reserved address */ +#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ + uint64_t res_addr; + uint32_t res_val; + /* Unified MMU. */ MicroBlazeMMU mmu; #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 96c2b71f7f..9e393cf217 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -193,7 +193,9 @@ static void mb_cpu_reset_hold(Object *obj) } memset(env, 0, offsetof(CPUMBState, end_reset_fields)); +#ifndef CONFIG_USER_ONLY env->res_addr = RES_ADDR_NONE; +#endif /* Disable stack protector. */ env->shr = ~0; diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c index 51705e4f5c..4daf8a2471 100644 --- a/target/microblaze/machine.c +++ b/target/microblaze/machine.c @@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = { VMSTATE_UINT32(iflags, CPUMBState), VMSTATE_UINT32(res_val, CPUMBState), - VMSTATE_UINTTL(res_addr, CPUMBState), + VMSTATE_UINT64(res_addr, CPUMBState), VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU), diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d6a42381bb..493850c544 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1872,7 +1872,9 @@ void mb_tcg_init(void) SP(iflags), SP(bvalue), SP(btarget), +#if !defined(CONFIG_USER_ONLY) SP(res_val), +#endif }; #undef R @@ -1883,6 +1885,9 @@ void mb_tcg_init(void) tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name); } - cpu_res_addr = - tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr"); +#if !defined(CONFIG_USER_ONLY) + cpu_res_addr = tcg_global_mem_new_i64(tcg_env, + offsetof(CPUMBState, res_addr), + "res_addr"); +#endif } -- 2.41.0