qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
	"Anton Johansson" <anjo@rev.ng>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-9.1 09/27] target/hppa: Convert to TCGCPUOps::get_cpu_state()
Date: Tue, 19 Mar 2024 16:42:38 +0100	[thread overview]
Message-ID: <20240319154258.71206-10-philmd@linaro.org> (raw)
In-Reply-To: <20240319154258.71206-1-philmd@linaro.org>

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hppa/cpu.h | 44 --------------------------------------------
 target/hppa/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 44 deletions(-)

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index cdb2904936..9bc54124c1 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -314,50 +314,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
 #define TB_FLAG_PRIV_SHIFT  8
 #define TB_FLAG_UNALIGN     0x400
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = env->psw_n * PSW_N;
-
-    /* TB lookup assumes that PC contains the complete virtual address.
-       If we leave space+offset separate, we'll get ITLB misses to an
-       incomplete virtual address.  This also means that we must separate
-       out current cpu privilege from the low bits of IAOQ_F.  */
-#ifdef CONFIG_USER_ONLY
-    *pc = env->iaoq_f & -4;
-    *cs_base = env->iaoq_b & -4;
-    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#else
-    /* ??? E, T, H, L, B bits need to be here, when implemented.  */
-    flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
-    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
-
-    *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
-                            env->iaoq_f & -4);
-    *cs_base = env->iasq_f;
-
-    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
-       low 32-bits of CS_BASE.  This will succeed for all direct branches,
-       which is the primary case we care about -- using goto_tb within a page.
-       Failure is indicated by a zero difference.  */
-    if (env->iasq_f == env->iasq_b) {
-        target_long diff = env->iaoq_b - env->iaoq_f;
-        if (diff == (int32_t)diff) {
-            *cs_base |= (uint32_t)diff;
-        }
-    }
-    if ((env->sr[4] == env->sr[5])
-        & (env->sr[4] == env->sr[6])
-        & (env->sr[4] == env->sr[7])) {
-        flags |= TB_FLAG_SR_SAME;
-    }
-#endif
-
-    *pflags = flags;
-}
-
 target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
 void cpu_hppa_loaded_fr0(CPUHPPAState *env);
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 3831cb6db2..f2dc1e79e9 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -89,6 +89,48 @@ static void hppa_restore_state_to_opc(CPUState *cs,
     cpu->env.psw_n = 0;
 }
 
+static void hppa_get_cpu_state(CPUHPPAState *env, vaddr *pc,
+                               uint64_t *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = env->psw_n * PSW_N;
+
+    /* TB lookup assumes that PC contains the complete virtual address.
+       If we leave space+offset separate, we'll get ITLB misses to an
+       incomplete virtual address.  This also means that we must separate
+       out current cpu privilege from the low bits of IAOQ_F.  */
+#ifdef CONFIG_USER_ONLY
+    *pc = env->iaoq_f & -4;
+    *cs_base = env->iaoq_b & -4;
+    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#else
+    /* ??? E, T, H, L, B bits need to be here, when implemented.  */
+    flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
+    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
+
+    *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
+                            env->iaoq_f & -4);
+    *cs_base = env->iasq_f;
+
+    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
+       low 32-bits of CS_BASE.  This will succeed for all direct branches,
+       which is the primary case we care about -- using goto_tb within a page.
+       Failure is indicated by a zero difference.  */
+    if (env->iasq_f == env->iasq_b) {
+        target_long diff = env->iaoq_b - env->iaoq_f;
+        if (diff == (int32_t)diff) {
+            *cs_base |= (uint32_t)diff;
+        }
+    }
+    if ((env->sr[4] == env->sr[5])
+        & (env->sr[4] == env->sr[6])
+        & (env->sr[4] == env->sr[7])) {
+        flags |= TB_FLAG_SR_SAME;
+    }
+#endif
+
+    *pflags = flags;
+}
+
 static bool hppa_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -186,6 +228,7 @@ static const TCGCPUOps hppa_tcg_ops = {
     .initialize = hppa_translate_init,
     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
     .restore_state_to_opc = hppa_restore_state_to_opc,
+    .get_cpu_state = hppa_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = hppa_cpu_tlb_fill,
-- 
2.41.0



  parent reply	other threads:[~2024-03-19 15:49 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-19 15:42 [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 01/27] accel/tcg: Ensure frontends define restore_state_to_opc handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 02/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 03/27] target/alpha: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 04/27] target/arm: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 05/27] target/arm: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 06/27] target/avr: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 07/27] target/cris: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 08/27] target/hexagon: " Philippe Mathieu-Daudé
2024-03-22 15:44   ` Brian Cain
2024-03-19 15:42 ` Philippe Mathieu-Daudé [this message]
2024-03-19 15:42 ` [PATCH-for-9.1 10/27] target/i386: " Philippe Mathieu-Daudé
2024-03-19 21:01   ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 11/27] target/loongarch: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 12/27] target/m68k: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 13/27] target/microblaze: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 14/27] target/mips: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 15/27] target/nios2: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 16/27] target/openrisc: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 17/27] target/ppc: Indent ppc_tcg_ops[] with 4 spaces Philippe Mathieu-Daudé
2024-03-20  4:49   ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-20  5:00   ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 19/27] target/riscv: " Philippe Mathieu-Daudé
2024-03-19 21:26   ` Daniel Henrique Barboza
2024-03-19 15:42 ` [PATCH-for-9.1 20/27] target/rx: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 21/27] target/s390x: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-20  6:38   ` Thomas Huth
2024-03-19 15:42 ` [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 21:05   ` Richard Henderson
2024-03-20  7:09     ` Philippe Mathieu-Daudé
2024-03-21  2:20       ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 23/27] target/sh4: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 24/27] target/sparc: " Philippe Mathieu-Daudé
2024-03-19 21:14   ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 25/27] target/tricore: " Philippe Mathieu-Daudé
2024-03-24  9:44   ` Bastian Koppelmann
2024-03-19 15:42 ` [PATCH-for-9.1 26/27] target/xtensa: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 27/27] accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE Philippe Mathieu-Daudé
2024-03-19 15:48 ` [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 16:01   ` Claudio Fontana
2024-03-19 21:16 ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240319154258.71206-10-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=anjo@rev.ng \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=qemu-s390x@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).