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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
	"Anton Johansson" <anjo@rev.ng>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Brian Cain" <bcain@quicinc.com>
Subject: [PATCH-for-9.1 08/27] target/hexagon: Convert to TCGCPUOps::get_cpu_state()
Date: Tue, 19 Mar 2024 16:42:37 +0100	[thread overview]
Message-ID: <20240319154258.71206-9-philmd@linaro.org> (raw)
In-Reply-To: <20240319154258.71206-1-philmd@linaro.org>

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hexagon/cpu.h | 14 --------------
 target/hexagon/cpu.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 935a9c3276..1d42c33827 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -134,20 +134,6 @@ struct ArchCPU {
 
 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    uint32_t hex_flags = 0;
-    *pc = env->gpr[HEX_REG_PC];
-    *cs_base = 0;
-    if (*pc == env->gpr[HEX_REG_SA0]) {
-        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
-    }
-    *flags = hex_flags;
-}
-
 typedef HexagonCPU ArchCPU;
 
 void hexagon_translate_init(void);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3a716b9be3..5e0a9441f2 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
     cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
 }
 
+static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc,
+                                  uint64_t *cs_base, uint32_t *flags)
+{
+    uint32_t hex_flags = 0;
+    *pc = env->gpr[HEX_REG_PC];
+    *cs_base = 0;
+    if (*pc == env->gpr[HEX_REG_SA0]) {
+        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
+    }
+    *flags = hex_flags;
+}
+
 static void hexagon_cpu_reset_hold(Object *obj)
 {
     CPUState *cs = CPU(obj);
@@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = {
     .initialize = hexagon_translate_init,
     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
     .restore_state_to_opc = hexagon_restore_state_to_opc,
+    .get_cpu_state = hexagon_get_cpu_state,
 };
 
 static void hexagon_cpu_class_init(ObjectClass *c, void *data)
-- 
2.41.0



  parent reply	other threads:[~2024-03-19 15:49 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-19 15:42 [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 01/27] accel/tcg: Ensure frontends define restore_state_to_opc handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 02/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 03/27] target/alpha: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 04/27] target/arm: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 05/27] target/arm: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 06/27] target/avr: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 07/27] target/cris: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` Philippe Mathieu-Daudé [this message]
2024-03-22 15:44   ` [PATCH-for-9.1 08/27] target/hexagon: " Brian Cain
2024-03-19 15:42 ` [PATCH-for-9.1 09/27] target/hppa: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 10/27] target/i386: " Philippe Mathieu-Daudé
2024-03-19 21:01   ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 11/27] target/loongarch: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 12/27] target/m68k: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 13/27] target/microblaze: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 14/27] target/mips: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 15/27] target/nios2: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 16/27] target/openrisc: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 17/27] target/ppc: Indent ppc_tcg_ops[] with 4 spaces Philippe Mathieu-Daudé
2024-03-20  4:49   ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-20  5:00   ` Nicholas Piggin
2024-03-19 15:42 ` [PATCH-for-9.1 19/27] target/riscv: " Philippe Mathieu-Daudé
2024-03-19 21:26   ` Daniel Henrique Barboza
2024-03-19 15:42 ` [PATCH-for-9.1 20/27] target/rx: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 21/27] target/s390x: Restrict TCG-specific declarations Philippe Mathieu-Daudé
2024-03-20  6:38   ` Thomas Huth
2024-03-19 15:42 ` [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state() Philippe Mathieu-Daudé
2024-03-19 21:05   ` Richard Henderson
2024-03-20  7:09     ` Philippe Mathieu-Daudé
2024-03-21  2:20       ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 23/27] target/sh4: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 24/27] target/sparc: " Philippe Mathieu-Daudé
2024-03-19 21:14   ` Richard Henderson
2024-03-19 15:42 ` [PATCH-for-9.1 25/27] target/tricore: " Philippe Mathieu-Daudé
2024-03-24  9:44   ` Bastian Koppelmann
2024-03-19 15:42 ` [PATCH-for-9.1 26/27] target/xtensa: " Philippe Mathieu-Daudé
2024-03-19 15:42 ` [PATCH-for-9.1 27/27] accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE Philippe Mathieu-Daudé
2024-03-19 15:48 ` [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler Philippe Mathieu-Daudé
2024-03-19 16:01   ` Claudio Fontana
2024-03-19 21:16 ` Richard Henderson

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