From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions
Date: Wed, 20 Mar 2024 15:25:03 +0800 [thread overview]
Message-ID: <20240320072709.1043227-3-max.chou@sifive.com> (raw)
In-Reply-To: <20240320072709.1043227-1-max.chou@sifive.com>
The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ef568e263d..6cb9bc9fde 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2331,6 +2331,7 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2370,6 +2371,7 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2402,6 +2404,7 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2441,6 +2444,7 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2941,6 +2945,7 @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_widen_check(s, a) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8);
}
--
2.31.1
next prev parent reply other threads:[~2024-03-20 7:27 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-20 7:25 [PATCH] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
2024-03-20 7:25 ` [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Max Chou
2024-03-20 20:12 ` Daniel Henrique Barboza
2024-03-20 7:25 ` Max Chou [this message]
2024-03-20 20:13 ` [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions Daniel Henrique Barboza
2024-03-20 7:25 ` [PATCH] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Max Chou
2024-03-20 20:13 ` Daniel Henrique Barboza
2024-03-20 7:25 ` [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Max Chou
2024-03-20 20:14 ` Daniel Henrique Barboza
2024-03-22 4:12 ` [PATCH] Fix fp16 checking in vector fp widen/narrow instructions Alistair Francis
2024-03-22 8:59 ` Max Chou
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