From: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com,
mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com,
pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com,
saif.abrar@linux.vnet.ibm.com
Subject: [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register
Date: Thu, 21 Mar 2024 05:04:21 -0500 [thread overview]
Message-ID: <20240321100422.5347-10-saif.abrar@linux.vnet.ibm.com> (raw)
In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com>
PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
---
hw/pci/pcie.c | 6 ++++++
include/standard-headers/linux/pci_regs.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 4b2f0805c6..e3081f6b84 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -212,6 +212,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset,
pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
+ pci_set_word(dev->wmask + pos + PCI_EXP_LNKCTL2,
+ PCI_EXP_LNKCTL2_TLS | PCI_EXP_LNKCTL2_ENTER_COMP |
+ PCI_EXP_LNKCTL2_TX_MARGIN | PCI_EXP_LNKCTL2_HASD |
+ PCI_EXP_LNKCTL2_MOD_COMP | PCI_EXP_LNKCTL2_COMP_SOS |
+ PCI_EXP_LNKCTL2_COMP_P_DE);
+
if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
/* read-only to behave like a 'NULL' Extended Capability Header */
pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index a39193213f..f743defe91 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -694,6 +694,9 @@
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
+#define PCI_EXP_LNKCTL2_MOD_COMP 0x0400 /* Enter Modified Compliance */
+#define PCI_EXP_LNKCTL2_COMP_SOS 0x0800 /* Compliance SOS */
+#define PCI_EXP_LNKCTL2_COMP_P_DE 0xF000 /* Compliance Preset/De-emphasis */
#define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */
#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
--
2.39.3
next prev parent reply other threads:[~2024-03-21 10:06 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-21 10:04 [PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5 Saif Abrar
2024-03-21 10:04 ` [PATCH 01/10] qtest/phb4: Add testbench for PHB4 Saif Abrar
2024-03-25 9:39 ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 02/10] pnv/phb4: Add reset logic to PHB4 Saif Abrar
2024-03-25 13:32 ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 03/10] pnv/phb4: Implement sticky reset logic in PHB4 Saif Abrar
2024-03-21 10:04 ` [PATCH 04/10] pnv/phb4: Implement read-only and write-only bits of registers Saif Abrar
2024-03-25 14:15 ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 05/10] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2024-03-25 13:58 ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers Saif Abrar
2024-03-21 10:04 ` [PATCH 07/10] pnv/phb4: Set link speed and width in the DLP training control register Saif Abrar
2024-03-25 13:36 ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 08/10] pnv/phb4: Implement IODA PCT table Saif Abrar
2024-03-25 13:35 ` Cédric Le Goater
2024-03-21 10:04 ` Saif Abrar [this message]
2024-03-25 13:35 ` [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register Cédric Le Goater
2024-03-25 14:37 ` Cornelia Huck
2024-03-21 10:04 ` [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Saif Abrar
2024-03-25 13:34 ` Cédric Le Goater
2024-03-27 9:59 ` Saif Abrar
2024-03-27 16:19 ` Cédric Le Goater
2024-03-28 9:31 ` Saif Abrar
2024-09-16 10:41 ` [PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5 Cédric Le Goater
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