[PATCH for-9.0 0/2] target/hppa: two more simple fixes

[PATCH for-9.0 0/2] target/hppa: two more simple fixes

[Richard Henderson]

Using the correct space for BE,L linkage might make the difference
for a cpu stress test.  I believe triggering this would require
something like

					f=(seg,ofs), b=(seg,ofs+4)
	be	0(sr1,r1)		f=(seg,ofs+4), b=(sr1,r1)
	be,l,n	0(sr2,r2),sr0,r31	f=(sr1,r1), b=(sr2,r2)

and then validating the contents of sr0 on return.

Linux only places B,GATE in the zero page, so amusingly there were
never any high bits to clobber.  But I can imagine HP-UX making
more use of gateway pages, and certainly a cpu stress test would.


r~


Richard Henderson (2):
  target/hppa: Fix BE,L set of sr0
  target/hppa: Fix B,GATE for wide mode

 target/hppa/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/2] target/hppa: Fix BE,L set of sr0

[Richard Henderson]

The return address comes from IA*Q_Next, and IASQ_Next
is always equal to IASQ_Back, not IASQ_Front.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 19594f917e..1766a63001 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3817,7 +3817,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
     load_spr(ctx, new_spc, a->sp);
     if (a->l) {
         copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var);
-        tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f);
+        tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b);
     }
     if (a->n && use_nullify_skip(ctx)) {
         copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp);
-- 
2.34.1

[PATCH 2/2] target/hppa: Fix B,GATE for wide mode

[Richard Henderson]

Do not clobber the high bits of the address by using a 32-bit deposit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1766a63001..f875d76a23 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3880,7 +3880,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
         }
         /* No change for non-gateway pages or for priv decrease.  */
         if (type >= 4 && type - 4 < ctx->privilege) {
-            dest = deposit32(dest, 0, 2, type - 4);
+            dest = deposit64(dest, 0, 2, type - 4);
         }
     } else {
         dest &= -4;  /* priv = 0 */
-- 
2.34.1

Re: [PATCH 2/2] target/hppa: Fix B,GATE for wide mode

[Philippe Mathieu-Daudé]

On 21/3/24 20:28, Richard Henderson wrote:
> Do not clobber the high bits of the address by using a 32-bit deposit.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/hppa/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 1766a63001..f875d76a23 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -3880,7 +3880,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
>           }
>           /* No change for non-gateway pages or for priv decrease.  */
>           if (type >= 4 && type - 4 < ctx->privilege) {
> -            dest = deposit32(dest, 0, 2, type - 4);
> +            dest = deposit64(dest, 0, 2, type - 4);
>           }
>       } else {
>           dest &= -4;  /* priv = 0 */

Fixes: 43e056522f ("target/hppa: Implement B,GATE insn")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 2/2] target/hppa: Fix B,GATE for wide mode

[Richard Henderson]

On 3/21/24 09:34, Philippe Mathieu-Daudé wrote:
> On 21/3/24 20:28, Richard Henderson wrote:
>> Do not clobber the high bits of the address by using a 32-bit deposit.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/hppa/translate.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
>> index 1766a63001..f875d76a23 100644
>> --- a/target/hppa/translate.c
>> +++ b/target/hppa/translate.c
>> @@ -3880,7 +3880,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
>>           }
>>           /* No change for non-gateway pages or for priv decrease.  */
>>           if (type >= 4 && type - 4 < ctx->privilege) {
>> -            dest = deposit32(dest, 0, 2, type - 4);
>> +            dest = deposit64(dest, 0, 2, type - 4);
>>           }
>>       } else {
>>           dest &= -4;  /* priv = 0 */
> 
> Fixes: 43e056522f ("target/hppa: Implement B,GATE insn")

Certainly not.  That predates hppa64 support by years.


r~

Re: [PATCH 2/2] target/hppa: Fix B,GATE for wide mode

[Helge Deller]

On 3/21/24 20:28, Richard Henderson wrote:
> Do not clobber the high bits of the address by using a 32-bit deposit.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Helge Deller <deller@gmx.de>

Helge

> ---
>   target/hppa/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 1766a63001..f875d76a23 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -3880,7 +3880,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
>           }
>           /* No change for non-gateway pages or for priv decrease.  */
>           if (type >= 4 && type - 4 < ctx->privilege) {
> -            dest = deposit32(dest, 0, 2, type - 4);
> +            dest = deposit64(dest, 0, 2, type - 4);
>           }
>       } else {
>           dest &= -4;  /* priv = 0 */