* [PATCH v2 1/4] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
2024-03-22 9:25 [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
@ 2024-03-22 9:25 ` Max Chou
2024-03-22 9:25 ` [PATCH v2 2/4] target/riscv: rvv: Check single width operator for vector fp widen instructions Max Chou
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Max Chou @ 2024-03-22 9:25 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Daniel Henrique Barboza, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
Richard Henderson
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7d84e7d8124..ef568e263d1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s)
}
}
+static bool require_rvfmin(DisasContext *s)
+{
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
+ return false;
+ }
+
+ switch (s->sew) {
+ case MO_16:
+ return s->cfg_ptr->ext_zvfhmin;
+ case MO_32:
+ return s->cfg_ptr->ext_zve32f;
+ default:
+ return false;
+ }
+}
+
static bool require_scale_rvf(DisasContext *s)
{
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s)
}
switch (s->sew) {
- case MO_8:
- return s->cfg_ptr->ext_zvfhmin;
case MO_16:
return s->cfg_ptr->ext_zve32f;
case MO_32:
@@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
+ require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
@@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
+ require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/4] target/riscv: rvv: Check single width operator for vector fp widen instructions
2024-03-22 9:25 [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
2024-03-22 9:25 ` [PATCH v2 1/4] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Max Chou
@ 2024-03-22 9:25 ` Max Chou
2024-03-22 9:25 ` [PATCH v2 3/4] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Max Chou
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Max Chou @ 2024-03-22 9:25 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Daniel Henrique Barboza, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
Richard Henderson
The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ef568e263d1..6cb9bc9fde8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2331,6 +2331,7 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2370,6 +2371,7 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2402,6 +2404,7 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2441,6 +2444,7 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
@@ -2941,6 +2945,7 @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_widen_check(s, a) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/4] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
2024-03-22 9:25 [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
2024-03-22 9:25 ` [PATCH v2 1/4] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Max Chou
2024-03-22 9:25 ` [PATCH v2 2/4] target/riscv: rvv: Check single width operator for vector fp widen instructions Max Chou
@ 2024-03-22 9:25 ` Max Chou
2024-03-22 9:25 ` [PATCH v2 4/4] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Max Chou
2024-05-14 5:22 ` [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Alistair Francis
4 siblings, 0 replies; 6+ messages in thread
From: Max Chou @ 2024-03-22 9:25 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Daniel Henrique Barboza, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
Richard Henderson
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6cb9bc9fde8..19059fea5f7 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2817,6 +2817,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
+ require_rvf(s) &&
require_scale_rvf(s) &&
(s->sew != MO_8);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 4/4] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
2024-03-22 9:25 [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
` (2 preceding siblings ...)
2024-03-22 9:25 ` [PATCH v2 3/4] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Max Chou
@ 2024-03-22 9:25 ` Max Chou
2024-05-14 5:22 ` [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Alistair Francis
4 siblings, 0 replies; 6+ messages in thread
From: Max Chou @ 2024-03-22 9:25 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Daniel Henrique Barboza, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
Richard Henderson
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 19059fea5f7..08c22f48cb4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2333,7 +2333,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
- (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
}
@@ -2373,7 +2372,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
- (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
@@ -2406,7 +2404,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
- (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
}
@@ -2446,7 +2443,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
require_scale_rvf(s) &&
- (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dd(s, a->rd, a->rs2, a->vm);
}
@@ -2704,8 +2700,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
require_rvfmin(s) &&
- require_scale_rvfmin(s) &&
- (s->sew != MO_8);
+ require_scale_rvfmin(s);
}
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
@@ -2810,16 +2805,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_rvfmin(s) &&
- require_scale_rvfmin(s) &&
- (s->sew != MO_8);
+ require_scale_rvfmin(s);
}
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_rvf(s) &&
- require_scale_rvf(s) &&
- (s->sew != MO_8);
+ require_scale_rvf(s);
}
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
@@ -2947,8 +2940,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_widen_check(s, a) &&
require_rvf(s) &&
- require_scale_rvf(s) &&
- (s->sew != MO_8);
+ require_scale_rvf(s);
}
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions
2024-03-22 9:25 [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Max Chou
` (3 preceding siblings ...)
2024-03-22 9:25 ` [PATCH v2 4/4] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Max Chou
@ 2024-05-14 5:22 ` Alistair Francis
4 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2024-05-14 5:22 UTC (permalink / raw)
To: Max Chou; +Cc: qemu-devel, qemu-riscv
On Fri, Mar 22, 2024 at 7:33 PM Max Chou <max.chou@sifive.com> wrote:
>
> When SEW is 16, we need to check whether the Zvfhmin is enabled for the
> single width operator for vector floating point widen/narrow
> instructions.
>
> The commits in this patchset fix the single width operator checking and
> remove the redudant SEW checking for vector floating point widen/narrow
> instructions.
>
> v2:
> Group patchset and rebase to the riscv-to-apply.next branch(commit 385e575)
>
>
> Thanks to those who have already reviewed:
>
> Daniel Henrique Barboza dbarboza@ventanamicro.com
> [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
> [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions
> [PATCH] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
> [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
>
>
> Max Chou (4):
> target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and
> vfncvt.f.f.w instructions
> target/riscv: rvv: Check single width operator for vector fp widen
> instructions
> target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
> target/riscv: rvv: Remove redudant SEW checking for vector fp
> narrow/widen instructions
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++---------
> 1 file changed, 28 insertions(+), 14 deletions(-)
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread