From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH 1/3] targt/hppa: Fix DCOR reconstruction of carry bits
Date: Sun, 24 Mar 2024 17:04:46 -1000 [thread overview]
Message-ID: <20240325030448.52110-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240325030448.52110-1-richard.henderson@linaro.org>
The carry bits for each nibble N are located in bit (N+1)*4,
so the shift by 3 was off by one. Furthermore, the carry bit
for the most significant carry bit is indeed located in bit 64,
which is located in a different storage word.
Use a double-word shift-right to reassemble into a single word
and place them all at bit 0 of their respective nibbles.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e041310207..a3f425d861 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2791,7 +2791,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
nullify_over(ctx);
tmp = tcg_temp_new_i64();
- tcg_gen_shri_i64(tmp, cpu_psw_cb, 3);
+ tcg_gen_extract2_i64(tmp, cpu_psw_cb, cpu_psw_cb_msb, 4);
if (!is_i) {
tcg_gen_not_i64(tmp, tmp);
}
--
2.34.1
next prev parent reply other threads:[~2024-03-25 3:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-25 3:04 [PATCH for-9.0 0/3] target/hppa: Fix DCOR, UADDCM conditions Richard Henderson
2024-03-25 3:04 ` Richard Henderson [this message]
2024-03-25 9:48 ` [PATCH 1/3] targt/hppa: Fix DCOR reconstruction of carry bits Helge Deller
2024-03-25 3:04 ` [PATCH 2/3] target/hppa: Optimize UADDCM with no condition Richard Henderson
2024-03-25 9:48 ` Helge Deller
2024-03-25 3:04 ` [PATCH 3/3] target/hppa: Fix unit carry conditions Richard Henderson
2024-03-25 10:36 ` Helge Deller
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