[PATCH-for-9.0? v2 4/8] hw/clock: Pass optional &bool argument to clock_set_hz()

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Pass optional &bool argument to clock_set_ns().
Since all callers ignore the return value, have
them use NULL.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/clock.h         | 8 ++------
 hw/arm/aspeed.c            | 2 +-
 hw/arm/fby35.c             | 2 +-
 hw/arm/mps2-tz.c           | 4 ++--
 hw/arm/mps2.c              | 4 ++--
 hw/arm/mps3r.c             | 2 +-
 hw/arm/msf2-som.c          | 2 +-
 hw/arm/musca.c             | 4 ++--
 hw/arm/netduino2.c         | 2 +-
 hw/arm/netduinoplus2.c     | 2 +-
 hw/arm/nrf51_soc.c         | 2 +-
 hw/arm/olimex-stm32-h405.c | 2 +-
 hw/arm/stm32vldiscovery.c  | 2 +-
 hw/arm/xilinx_zynq.c       | 2 +-
 hw/char/cadence_uart.c     | 4 ++--
 15 files changed, 20 insertions(+), 24 deletions(-)

diff --git a/include/hw/clock.h b/include/hw/clock.h
index 94ed5ba6e6..f0ac410fc8 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@@ -186,13 +186,9 @@ static inline bool clock_has_source(const Clock *clk)
  */
 void clock_set(Clock *clk, uint64_t period, bool *changed);
 
-static inline bool clock_set_hz(Clock *clk, unsigned hz)
+static inline void clock_set_hz(Clock *clk, unsigned hz, bool *changed)
 {
-    bool changed = false;
-
-    clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz), &changed);
-
-    return changed;
+    clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz), changed);
 }
 
 static inline void clock_set_ns(Clock *clk, unsigned ns, bool *changed)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8854581ca8..7e4ed71e9f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1521,7 +1521,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
     Clock *sysclk;
 
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(sysclk, SYSCLK_FRQ);
+    clock_set_hz(sysclk, SYSCLK_FRQ, NULL);
 
     bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
     object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index c9964bd283..dd4abdd768 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -119,7 +119,7 @@ static void fby35_bic_init(Fby35State *s)
     AspeedSoCState *soc;
 
     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
-    clock_set_hz(s->bic_sysclk, 200000000ULL);
+    clock_set_hz(s->bic_sysclk, 200000000ULL, NULL);
 
     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
     soc = ASPEED_SOC(&s->bic);
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index a2d18afd79..015db74ab8 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -818,9 +818,9 @@ static void mps2tz_common_init(MachineState *machine)
 
     /* These clocks don't need migration because they are fixed-frequency */
     mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(mms->sysclk, mmc->sysclk_frq);
+    clock_set_hz(mms->sysclk, mmc->sysclk_frq, NULL);
     mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
-    clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
+    clock_set_hz(mms->s32kclk, S32KCLK_FRQ, NULL);
 
     object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
                             mmc->armsse_type);
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 50919ee46d..7176305239 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -151,10 +151,10 @@ static void mps2_common_init(MachineState *machine)
 
     /* This clock doesn't need migration because it is fixed-frequency */
     mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+    clock_set_hz(mms->sysclk, SYSCLK_FRQ, NULL);
 
     mms->refclk = clock_new(OBJECT(machine), "REFCLK");
-    clock_set_hz(mms->refclk, REFCLK_FRQ);
+    clock_set_hz(mms->refclk, REFCLK_FRQ, NULL);
 
     /* The FPGA images have an odd combination of different RAMs,
      * because in hardware they are different implementations and
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 4d55a6564c..84f1f9d3a2 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -360,7 +360,7 @@ static void mps3r_common_init(MachineState *machine)
     QList *oscclk;
 
     mms->clk = clock_new(OBJECT(machine), "CLK");
-    clock_set_hz(mms->clk, CLK_FRQ);
+    clock_set_hz(mms->clk, CLK_FRQ, NULL);
 
     for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
         MemoryRegion *mr = mr_for_raminfo(mms, ri);
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 5c415abe85..420c0ae332 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -71,7 +71,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
      */
     /* This clock doesn't need migration because it is fixed-frequency */
     m3clk = clock_new(OBJECT(machine), "m3clk");
-    clock_set_hz(m3clk, 142 * 1000000);
+    clock_set_hz(m3clk, 142 * 1000000, NULL);
     qdev_connect_clock_in(dev, "m3clk", m3clk);
     qdev_prop_set_uint32(dev, "apb0div", 2);
     qdev_prop_set_uint32(dev, "apb1div", 2);
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index e2c9d49af5..6fdcb76dfa 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -366,9 +366,9 @@ static void musca_init(MachineState *machine)
     assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
 
     mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+    clock_set_hz(mms->sysclk, SYSCLK_FRQ, NULL);
     mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
-    clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
+    clock_set_hz(mms->s32kclk, S32KCLK_FRQ, NULL);
 
     object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
                             TYPE_SSE200);
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 8b1a9a2437..49a3ee2c47 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -41,7 +41,7 @@ static void netduino2_init(MachineState *machine)
 
     /* This clock doesn't need migration because it is fixed-frequency */
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(sysclk, SYSCLK_FRQ);
+    clock_set_hz(sysclk, SYSCLK_FRQ, NULL);
 
     dev = qdev_new(TYPE_STM32F205_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index bccd100354..30d9c0410d 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -41,7 +41,7 @@ static void netduinoplus2_init(MachineState *machine)
 
     /* This clock doesn't need migration because it is fixed-frequency */
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(sysclk, SYSCLK_FRQ);
+    clock_set_hz(sysclk, SYSCLK_FRQ, NULL);
 
     dev = qdev_new(TYPE_STM32F405_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index ac53441630..9aebb98934 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -75,7 +75,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
     /* This clock doesn't need migration because it is fixed-frequency */
-    clock_set_hz(s->sysclk, HCLK_FRQ);
+    clock_set_hz(s->sysclk, HCLK_FRQ, NULL);
     qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
     /*
      * This SoC has no systick device, so don't connect refclk.
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 4ad7b043be..394875608a 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -44,7 +44,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
 
     /* This clock doesn't need migration because it is fixed-frequency */
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(sysclk, SYSCLK_FRQ);
+    clock_set_hz(sysclk, SYSCLK_FRQ, NULL);
 
     dev = qdev_new(TYPE_STM32F405_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index cc41935160..4be626e878 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -44,7 +44,7 @@ static void stm32vldiscovery_init(MachineState *machine)
 
     /* This clock doesn't need migration because it is fixed-frequency */
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-    clock_set_hz(sysclk, SYSCLK_FRQ);
+    clock_set_hz(sysclk, SYSCLK_FRQ, NULL);
 
     dev = qdev_new(TYPE_STM32F100_SOC);
     object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index fc3abcbe88..1fd13caa58 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -228,7 +228,7 @@ static void zynq_init(MachineState *machine)
     object_property_add_child(OBJECT(zynq_machine), "ps_clk",
                               OBJECT(zynq_machine->ps_clk));
     object_unref(OBJECT(zynq_machine->ps_clk));
-    clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
+    clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY, NULL);
 
     /* Create slcr, keep a pointer to connect clocks */
     slcr = qdev_new("xilinx-zynq_slcr");
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index db31d7cc85..4619209af4 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -566,7 +566,7 @@ static void cadence_uart_init(Object *obj)
     s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
                                    cadence_uart_refclk_update, s, ClockUpdate);
     /* initialize the frequency in case the clock remains unconnected */
-    clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
+    clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK, NULL);
 
     s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 }
@@ -576,7 +576,7 @@ static int cadence_uart_pre_load(void *opaque)
     CadenceUARTState *s = opaque;
 
     /* the frequency will be overridden if the refclk field is present */
-    clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
+    clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK, NULL);
     return 0;
 }
 
-- 
2.41.0