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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9-20020a170903230900b001e14807c7dfsm247424plh.86.2024.03.27.19.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 19:23:48 -0700 (PDT) From: Jason Chien To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jason Chien Subject: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions Date: Thu, 28 Mar 2024 10:23:09 +0800 Message-ID: <20240328022343.6871-1-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=jason.chien@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch series adds the support for Zve32x and Zvx64x and makes vector registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. v2: Rebase onto riscv-to-apply.next (commit 385e575). v3: Spuash patch 2 into patch 1. Spuash patch 4 into patch 3. Jason Chien (3): target/riscv: Add support for Zve32x extension target/riscv: Add support for Zve64x extension target/riscv: Relax vector register check in RISCV gdbstub target/riscv/cpu.c | 4 +++ target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/gdbstub.c | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 +-- target/riscv/tcg/tcg-cpu.c | 33 ++++++++++++++----------- 7 files changed, 30 insertions(+), 19 deletions(-) -- 2.43.2