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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Helge Deller <deller@kernel.org>, Helge Deller <deller@gmx.de>
Subject: [PULL 17/18] target/hppa: Add diag instructions to set/restore shadow registers
Date: Fri, 29 Mar 2024 12:31:10 -1000	[thread overview]
Message-ID: <20240329223111.1735826-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org>

From: Helge Deller <deller@kernel.org>

The 32-bit PA-7300LC (PCX-L2) CPU and the 64-bit PA8700 (PCX-W2) CPU
use different diag instructions to save or restore the CPU registers
to/from the shadow registers.

Implement those per-CPU architecture diag instructions to fix those
parts of the HP ODE testcases (L2DIAG and WDIAG, section 1) which test
the shadow registers.

Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Use decodetree to distinguish cases]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
---
 target/hppa/insns.decode | 10 ++++++++++
 target/hppa/translate.c  | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 9f6ffd8e2c..71074a64c1 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -65,6 +65,8 @@
 # Argument set definitions
 ####
 
+&empty
+
 # All insns that need to form a virtual address should use this set.
 &ldst           t b x disp sp m scale size
 
@@ -638,6 +640,14 @@ xmpyu           001110 ..... ..... 010 .0111 .00 t:5    r1=%ra64 r2=%rb64
   [
     diag_btlb               000101 00 0000 0000 0000 0001 0000 0000
     diag_cout               000101 00 0000 0000 0000 0001 0000 0001
+
+    # For 32-bit PA-7300LC (PCX-L2)
+    diag_getshadowregs_pa1  000101 00 0000 0000 0001 1010 0000 0000
+    diag_putshadowregs_pa1  000101 00 0000 0000 0001 1010 0100 0000
+
+    # For 64-bit PA8700 (PCX-W2)
+    diag_getshadowregs_pa2  000101 00 0111 1000 0001 1000 0100 0000
+    diag_putshadowregs_pa2  000101 00 0111 0000 0001 1000 0100 0000
   ]
   diag_unimp                000101 i:26
 }
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 42dd3f2c8d..143818c2d9 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2399,6 +2399,20 @@ static bool do_getshadowregs(DisasContext *ctx)
     return nullify_end(ctx);
 }
 
+static bool do_putshadowregs(DisasContext *ctx)
+{
+    CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+    nullify_over(ctx);
+    tcg_gen_st_i64(cpu_gr[1], tcg_env, offsetof(CPUHPPAState, shadow[0]));
+    tcg_gen_st_i64(cpu_gr[8], tcg_env, offsetof(CPUHPPAState, shadow[1]));
+    tcg_gen_st_i64(cpu_gr[9], tcg_env, offsetof(CPUHPPAState, shadow[2]));
+    tcg_gen_st_i64(cpu_gr[16], tcg_env, offsetof(CPUHPPAState, shadow[3]));
+    tcg_gen_st_i64(cpu_gr[17], tcg_env, offsetof(CPUHPPAState, shadow[4]));
+    tcg_gen_st_i64(cpu_gr[24], tcg_env, offsetof(CPUHPPAState, shadow[5]));
+    tcg_gen_st_i64(cpu_gr[25], tcg_env, offsetof(CPUHPPAState, shadow[6]));
+    return nullify_end(ctx);
+}
+
 static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a)
 {
     return do_getshadowregs(ctx);
@@ -4594,6 +4608,26 @@ static bool trans_diag_cout(DisasContext *ctx, arg_diag_cout *a)
 #endif
 }
 
+static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a)
+{
+    return !ctx->is_pa20 && do_getshadowregs(ctx);
+}
+
+static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a)
+{
+    return ctx->is_pa20 && do_getshadowregs(ctx);
+}
+
+static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a)
+{
+    return !ctx->is_pa20 && do_putshadowregs(ctx);
+}
+
+static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a)
+{
+    return ctx->is_pa20 && do_putshadowregs(ctx);
+}
+
 static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a)
 {
     CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
-- 
2.34.1



  parent reply	other threads:[~2024-03-29 22:33 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-29 22:30 [PULL 00/18] target/hppa patch queue Richard Henderson
2024-03-29 22:30 ` [PULL 01/18] target/hppa: Fix BE,L set of sr0 Richard Henderson
2024-03-29 22:30 ` [PULL 02/18] target/hppa: Fix B,GATE for wide mode Richard Henderson
2024-03-29 22:30 ` [PULL 03/18] target/hppa: Handle unit conditions " Richard Henderson
2024-03-29 22:30 ` [PULL 04/18] target/hppa: Fix ADD/SUB trap on overflow for narrow mode Richard Henderson
2024-03-29 22:30 ` [PULL 05/18] target/hppa: Mark interval timer write as io Richard Henderson
2024-03-29 22:30 ` [PULL 06/18] target/hppa: Tidy read of interval timer Richard Henderson
2024-03-29 22:31 ` [PULL 07/18] target/hppa: Fix EIRR, EIEM versus icount Richard Henderson
2024-03-29 22:31 ` [PULL 08/18] target/hppa: Use gva_offset_mask() everywhere Richard Henderson
2024-03-29 22:31 ` [PULL 09/18] target/hppa: Fix DCOR reconstruction of carry bits Richard Henderson
2024-03-29 22:31 ` [PULL 10/18] target/hppa: Optimize UADDCM with no condition Richard Henderson
2024-03-29 22:31 ` [PULL 11/18] target/hppa: Fix unit carry conditions Richard Henderson
2024-03-29 22:31 ` [PULL 12/18] target/hppa: Squash d for pa1.x during decode Richard Henderson
2024-03-29 22:31 ` [PULL 13/18] target/hppa: Replace c with uv in do_cond Richard Henderson
2024-03-29 22:31 ` [PULL 14/18] target/hppa: Fix overflow computation for shladd Richard Henderson
2024-03-29 22:31 ` [PULL 15/18] target/hppa: Generate getshadowregs inline Richard Henderson
2024-03-29 22:31 ` [PULL 16/18] target/hppa: Move diag argument handling to decodetree Richard Henderson
2024-03-29 22:31 ` Richard Henderson [this message]
2024-03-29 22:31 ` [PULL 18/18] target/hppa: Clear psw_n for BE on use_nullify_skip path Richard Henderson
2024-04-01 12:09 ` [PULL 00/18] target/hppa patch queue Peter Maydell

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