From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Sven Schnelle <svens@stackframe.org>
Subject: [PULL 03/18] target/hppa: Handle unit conditions for wide mode
Date: Fri, 29 Mar 2024 12:30:56 -1000 [thread overview]
Message-ID: <20240329223111.1735826-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240329223111.1735826-1-richard.henderson@linaro.org>
From: Sven Schnelle <svens@stackframe.org>
Wide mode provides two more conditions, add them.
Fixes: 59963d8fdf42 ("target/hppa: Pass d to do_unit_cond")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-1-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index f875d76a23..2cb91956da 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -967,11 +967,22 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
switch (cf >> 1) {
case 0: /* never / TR */
- case 1: /* undefined */
- case 5: /* undefined */
cond = cond_make_f();
break;
+ case 1: /* SBW / NBW */
+ if (d) {
+ tmp = tcg_temp_new_i64();
+ tcg_gen_subi_i64(tmp, res, d_repl * 0x00000001u);
+ tcg_gen_andc_i64(tmp, tmp, res);
+ tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80000000u);
+ cond = cond_make_0(TCG_COND_NE, tmp);
+ } else {
+ /* undefined */
+ cond = cond_make_f();
+ }
+ break;
+
case 2: /* SBZ / NBZ */
/* See hasless(v,1) from
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
@@ -996,6 +1007,16 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
cond = cond_make_0(TCG_COND_NE, cb);
break;
+ case 5: /* SWC / NWC */
+ if (d) {
+ tcg_gen_andi_i64(cb, cb, d_repl * 0x80000000u);
+ cond = cond_make_0(TCG_COND_NE, cb);
+ } else {
+ /* undefined */
+ cond = cond_make_f();
+ }
+ break;
+
case 6: /* SBC / NBC */
tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
--
2.34.1
next prev parent reply other threads:[~2024-03-29 22:32 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 22:30 [PULL 00/18] target/hppa patch queue Richard Henderson
2024-03-29 22:30 ` [PULL 01/18] target/hppa: Fix BE,L set of sr0 Richard Henderson
2024-03-29 22:30 ` [PULL 02/18] target/hppa: Fix B,GATE for wide mode Richard Henderson
2024-03-29 22:30 ` Richard Henderson [this message]
2024-03-29 22:30 ` [PULL 04/18] target/hppa: Fix ADD/SUB trap on overflow for narrow mode Richard Henderson
2024-03-29 22:30 ` [PULL 05/18] target/hppa: Mark interval timer write as io Richard Henderson
2024-03-29 22:30 ` [PULL 06/18] target/hppa: Tidy read of interval timer Richard Henderson
2024-03-29 22:31 ` [PULL 07/18] target/hppa: Fix EIRR, EIEM versus icount Richard Henderson
2024-03-29 22:31 ` [PULL 08/18] target/hppa: Use gva_offset_mask() everywhere Richard Henderson
2024-03-29 22:31 ` [PULL 09/18] target/hppa: Fix DCOR reconstruction of carry bits Richard Henderson
2024-03-29 22:31 ` [PULL 10/18] target/hppa: Optimize UADDCM with no condition Richard Henderson
2024-03-29 22:31 ` [PULL 11/18] target/hppa: Fix unit carry conditions Richard Henderson
2024-03-29 22:31 ` [PULL 12/18] target/hppa: Squash d for pa1.x during decode Richard Henderson
2024-03-29 22:31 ` [PULL 13/18] target/hppa: Replace c with uv in do_cond Richard Henderson
2024-03-29 22:31 ` [PULL 14/18] target/hppa: Fix overflow computation for shladd Richard Henderson
2024-03-29 22:31 ` [PULL 15/18] target/hppa: Generate getshadowregs inline Richard Henderson
2024-03-29 22:31 ` [PULL 16/18] target/hppa: Move diag argument handling to decodetree Richard Henderson
2024-03-29 22:31 ` [PULL 17/18] target/hppa: Add diag instructions to set/restore shadow registers Richard Henderson
2024-03-29 22:31 ` [PULL 18/18] target/hppa: Clear psw_n for BE on use_nullify_skip path Richard Henderson
2024-04-01 12:09 ` [PULL 00/18] target/hppa patch queue Peter Maydell
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