From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: <qemu-devel@nongnu.org>, "Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Xiong Yining <xiongyining1480@phytium.com.cn>,
Chen Baozi <chenbaozi@phytium.com.cn>
Subject: Re: How to use pxb-pcie in correct way?
Date: Tue, 9 Apr 2024 16:14:27 +0100 [thread overview]
Message-ID: <20240409161427.00001b1c@Huawei.com> (raw)
In-Reply-To: <8b9b96e1-faaa-4866-aeb9-c439d5f83139@linaro.org>
On Mon, 8 Apr 2024 13:58:00 +0200
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> wrote:
> For quite a while I am experimenting with PCI Express setup on SBSA-Ref
> system. And finally decided to write.
>
> We want to play with NUMA setup and "pxb-pcie" can be assigned to NUMA
> node other than cpu0 one. But adding it makes other cards dissapear...
>
> When I boot sbsa-ref I have plain PCIe setup:
>
> (qemu) info pci
> Bus 0, device 0, function 0:
> Host bridge: PCI device 1b36:0008
> PCI subsystem 1af4:1100
> id ""
> Bus 0, device 1, function 0:
> Ethernet controller: PCI device 8086:10d3
> PCI subsystem 8086:0000
> IRQ 255, pin A
> BAR0: 32 bit memory at 0xffffffffffffffff [0x0001fffe].
> BAR1: 32 bit memory at 0xffffffffffffffff [0x0001fffe].
> BAR2: I/O at 0xffffffffffffffff [0x001e].
> BAR3: 32 bit memory at 0xffffffffffffffff [0x00003ffe].
> BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe].
> id ""
> Bus 0, device 2, function 0:
> Display controller: PCI device 1234:1111
> PCI subsystem 1af4:1100
> BAR0: 32 bit prefetchable memory at 0x80000000 [0x80ffffff].
> BAR2: 32 bit memory at 0x81084000 [0x81084fff].
> BAR6: 32 bit memory at 0xffffffffffffffff [0x00007ffe].
> id ""
>
> Adding extra PCIe card works fine - both just "igb" and "igb" with
> "pcie-root-port".
>
> But adding "pcie-root-port" + "igb" and then "pxb-pcie" makes "igb"
> dissapear:
>
> ../code/qemu/build/qemu-system-aarch64
> -monitor telnet::45454,server,nowait
> -serial stdio
> -device pcie-root-port,id=ULyWl,slot=0,chassis=0
> -device igb,bus=ULyWl
> -device pxb-pcie,bus_nr=1
That's setting the base bus number to 1. Very likely to clash with the bus
number for the bus below the root port.
Set it to bu_nr=128 or something like that.
There is no sanity checking for PXBs because the bus enumeration is
an EDK2 problem in general - short of enumerating the buses in QEMU
there isn't a way for it to tell.
J
prev parent reply other threads:[~2024-04-09 15:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-08 11:58 How to use pxb-pcie in correct way? Marcin Juszkiewicz
2024-04-09 15:14 ` Jonathan Cameron via [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240409161427.00001b1c@Huawei.com \
--to=qemu-devel@nongnu.org \
--cc=Jonathan.Cameron@Huawei.com \
--cc=ardb+tianocore@kernel.org \
--cc=chenbaozi@phytium.com.cn \
--cc=marcel.apfelbaum@gmail.com \
--cc=marcin.juszkiewicz@linaro.org \
--cc=mst@redhat.com \
--cc=quic_llindhol@quicinc.com \
--cc=xiongyining1480@phytium.com.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).