From: Huang Tao <eric.huang@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com,
dbarboza@ventanamicro.com, liwei1518@gmail.com,
bin.meng@windriver.com, alistair.francis@wdc.com,
palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com>
Subject: [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector
Date: Fri, 12 Apr 2024 15:37:02 +0800 [thread overview]
Message-ID: <20240412073735.76413-33-eric.huang@linux.alibaba.com> (raw)
In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com>
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 9 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 6 ++++--
target/riscv/vector_helper.c | 8 ++++----
target/riscv/vector_internals.h | 6 ++++++
target/riscv/xtheadvector_helper.c | 19 +++++++++++++++++++
5 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index aab2979328..85962f7253 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1935,3 +1935,12 @@ DEF_HELPER_6(th_vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 59da1e4b3f..df653bd1c9 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1717,14 +1717,16 @@ GEN_OPIVX_TRANS_TH(th_vaadd_vx, opivx_check_th)
GEN_OPIVX_TRANS_TH(th_vasub_vx, opivx_check_th)
GEN_OPIVI_TRANS_TH(th_vaadd_vi, IMM_SX, th_vaadd_vx, opivx_check_th)
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+GEN_OPIVV_TRANS_TH(th_vsmul_vv, opivv_check_th)
+GEN_OPIVX_TRANS_TH(th_vsmul_vx, opivx_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vsmul_vv)
-TH_TRANS_STUB(th_vsmul_vx)
TH_TRANS_STUB(th_vwsmaccu_vv)
TH_TRANS_STUB(th_vwsmaccu_vx)
TH_TRANS_STUB(th_vwsmacc_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ea1e449174..331a9a9c7a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2474,7 +2474,7 @@ GEN_VEXT_VX_RM(vasubu_vx_w, 4)
GEN_VEXT_VX_RM(vasubu_vx_d, 8)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
-static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
uint8_t round;
int16_t res;
@@ -2494,7 +2494,7 @@ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
}
}
-static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
{
uint8_t round;
int32_t res;
@@ -2514,7 +2514,7 @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
}
}
-static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
uint8_t round;
int64_t res;
@@ -2534,7 +2534,7 @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
}
}
-static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
{
uint8_t round;
uint64_t hi_64, lo_64;
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 19f174f4c8..c76ff5abac 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -308,4 +308,10 @@ int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b);
int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b);
int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b);
int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b);
+
+int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b);
+int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b);
+int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b);
+int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b);
+
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index 06ac5940b7..e4acb4d176 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2294,3 +2294,22 @@ GEN_TH_VX_RM(th_vasub_vx_b, 1, 1, clearb_th)
GEN_TH_VX_RM(th_vasub_vx_h, 2, 2, clearh_th)
GEN_TH_VX_RM(th_vasub_vx_w, 4, 4, clearl_th)
GEN_TH_VX_RM(th_vasub_vx_d, 8, 8, clearq_th)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+THCALL(TH_OPIVV2_RM, th_vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
+THCALL(TH_OPIVV2_RM, th_vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
+THCALL(TH_OPIVV2_RM, th_vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
+THCALL(TH_OPIVV2_RM, th_vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
+GEN_TH_VV_RM(th_vsmul_vv_b, 1, 1, clearb_th)
+GEN_TH_VV_RM(th_vsmul_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_RM(th_vsmul_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_RM(th_vsmul_vv_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVX2_RM, th_vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
+THCALL(TH_OPIVX2_RM, th_vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
+THCALL(TH_OPIVX2_RM, th_vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
+THCALL(TH_OPIVX2_RM, th_vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
+GEN_TH_VX_RM(th_vsmul_vx_b, 1, 1, clearb_th)
+GEN_TH_VX_RM(th_vsmul_vx_h, 2, 2, clearh_th)
+GEN_TH_VX_RM(th_vsmul_vx_w, 4, 4, clearl_th)
+GEN_TH_VX_RM(th_vsmul_vx_d, 8, 8, clearq_th)
--
2.44.0
next prev parent reply other threads:[~2024-04-12 8:43 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 7:36 [PATCH 00/65]target/riscv: Support XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Huang Tao
2024-04-12 7:36 ` [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs Huang Tao
2024-04-12 7:36 ` [PATCH 03/65] target/riscv: Add properties for XTheadVector extension Huang Tao
2024-04-12 7:36 ` [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 05/65] target/riscv: Add mlen in DisasContext Huang Tao
2024-04-12 7:36 ` [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector Huang Tao
2024-04-12 7:36 ` [PATCH 07/65] target/riscv: implement th.vsetvl{i} " Huang Tao
2024-04-12 7:36 ` [PATCH 08/65] target/riscv: Add strided load instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 09/65] target/riscv: Add strided store " Huang Tao
2024-04-12 7:36 ` [PATCH 10/65] target/riscv: Add unit-stride load " Huang Tao
2024-04-12 7:36 ` [PATCH 11/65] target/riscv: Add unit-stride store " Huang Tao
2024-04-12 7:36 ` [PATCH 12/65] target/riscv: Add indexed load " Huang Tao
2024-04-12 7:36 ` [PATCH 13/65] target/riscv: Add indexed store " Huang Tao
2024-04-12 7:36 ` [PATCH 14/65] target/riscv: Add unit-stride fault-only-first " Huang Tao
2024-04-12 7:36 ` [PATCH 15/65] target/riscv: Add vector amo operations " Huang Tao
2024-04-12 7:36 ` [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions " Huang Tao
2024-04-12 7:36 ` [PATCH 17/65] target/riscv: Add widening integer add/subtract " Huang Tao
2024-04-12 7:36 ` [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow " Huang Tao
2024-04-12 7:36 ` [PATCH 19/65] target/riscv: Add bitwise logical " Huang Tao
2024-04-12 7:36 ` [PATCH 20/65] target/riscv: Add single-width bit shift " Huang Tao
2024-04-12 7:36 ` [PATCH 21/65] target/riscv: Add narrowing integer right " Huang Tao
2024-04-12 7:36 ` [PATCH 22/65] target/riscv: Add integer compare " Huang Tao
2024-04-12 7:36 ` [PATCH 23/65] target/riscv: Add integer min/max " Huang Tao
2024-04-12 7:36 ` [PATCH 24/65] target/riscv: Add single-width integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 25/65] target/riscv: Add integer divide " Huang Tao
2024-04-12 7:36 ` [PATCH 26/65] target/riscv: Add widening integer multiply " Huang Tao
2024-04-12 7:36 ` [PATCH 27/65] target/riscv: Add single-width integer multiply-add " Huang Tao
2024-04-12 7:36 ` [PATCH 28/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:36 ` [PATCH 29/65] target/riscv: Add integer merge and move " Huang Tao
2024-04-12 7:37 ` [PATCH 30/65] target/riscv: Add single-width saturating add and sub " Huang Tao
2024-04-12 7:37 ` [PATCH 31/65] target/riscv: Add single-width average " Huang Tao
2024-04-12 7:37 ` Huang Tao [this message]
2024-04-12 7:37 ` [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 34/65] target/riscv: Add single-width scaling shift " Huang Tao
2024-04-12 7:37 ` [PATCH 35/65] target/riscv: Add narrowing fixed-point clip " Huang Tao
2024-04-12 7:37 ` [PATCH 36/65] target/riscv: Add single-width floating-point add/sub " Huang Tao
2024-04-12 7:37 ` [PATCH 37/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide " Huang Tao
2024-04-12 7:37 ` [PATCH 39/65] target/riscv: Add widening floating-point multiply " Huang Tao
2024-04-12 7:37 ` [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add " Huang Tao
2024-04-12 7:37 ` [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add " Huang Tao
2024-04-12 7:37 ` [PATCH 42/65] target/riscv: Add floating-pointing square-root " Huang Tao
2024-04-12 7:37 ` [PATCH 43/65] target/riscv: Add floating-point MIN/MAX " Huang Tao
2024-04-12 7:37 ` [PATCH 44/65] target/riscv: Add floating-point sign-injection " Huang Tao
2024-04-12 7:37 ` [PATCH 45/65] target/riscv: Add floating-point compare " Huang Tao
2024-04-12 7:37 ` [PATCH 46/65] target/riscv: Add floating-point classify and merge " Huang Tao
2024-04-12 7:37 ` [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert " Huang Tao
2024-04-12 7:37 ` [PATCH 48/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 49/65] target/riscv: Add narrowing " Huang Tao
2024-04-12 7:37 ` [PATCH 50/65] target/riscv: Add single-width integer reduction " Huang Tao
2024-04-12 7:37 ` [PATCH 51/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 52/65] target/riscv: Add single-width floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 53/65] target/riscv: Add widening " Huang Tao
2024-04-12 7:37 ` [PATCH 54/65] target/riscv: Add mask-register logical " Huang Tao
2024-04-12 7:37 ` [PATCH 55/65] target/riscv: Add vector mask population count vmpopc " Huang Tao
2024-04-12 7:37 ` [PATCH 56/65] target/riscv: Add th.vmfirst.m " Huang Tao
2024-04-12 7:37 ` [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions " Huang Tao
2024-04-12 7:37 ` [PATCH 58/65] target/riscv: Add vector iota instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 59/65] target/riscv: Add vector element index " Huang Tao
2024-04-12 7:37 ` [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions " Huang Tao
2024-04-12 7:37 ` [PATCH 61/65] target/riscv: Add floating-point " Huang Tao
2024-04-12 7:37 ` [PATCH 62/65] target/riscv: Add vector slide " Huang Tao
2024-04-12 7:37 ` [PATCH 63/65] target/riscv: Add vector register gather " Huang Tao
2024-04-12 7:37 ` [PATCH 64/65] target/riscv: Add vector compress instruction " Huang Tao
2024-04-12 7:37 ` [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906 Huang Tao
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